4.7 Instruction Descriptions (N to XORWF)


NEG		Negate Accumulators
Syntax:	{label:}	NEG	A
			B






Operands:	None
Operation:	if (NEGAB A) then -ACCA → ACCA if (NEGAB B) then -ACCB → ACCB
Status Affected:	OA, SA or OB, SB
Encoding:	`0111`	`001A`	`UUUU`	`1010`
Description:	Compute the 2’s complement of the contents of the specified accumulator and place the result back into the specified accumulator. The ‘A’ bit specifies the selected accumulator. OA and SA are affected if AccA is selected. OB and SB are affected if AccB is selected.
I-Words:	0.5
Cycles:	1


NEG	A

Before execution		After execution
ACCA	0x00_4000_0000_0000_0000	ACCA	0xFF_C000_0000_0000_0000


Example 1:	`NEG A ; Negate ACCA` `; Store result to ACCA` `; CORCON = 0x0000 (no saturation)`
		Before Instruction			After Instruction
ACCA		00 3290 59C8		ACCA	FF CD6F A638
CORCON		0000	CORCON		0000
	SR	0000		SR	0000


Example 2:	`NEG B ; Negate ACCB` `; Store result to ACCB` `; CORCON = 0x00C0 (normal saturation)`
		Before Instruction			After Instruction
ACCB		FF F230 10DC	ACCB		00 0DCF EF24
CORCON		00C0	CORCON		00C0
	SR	0000		SR	0000


NEG		Negate f
Syntax:	{label:}	NEG.b	f	{,Wnd}	{,WREG}
		NEG.bz
		NEG{.w}
		NEG.l




Operands:	f ∈ [0 ... 64KB]; Wnd ∈ [W0 ... W14]
Operation:	(f) + 1 → destination designated by D
Status Affected:	C, N, OV, Z
Encoding:	`1101`	`101L`	`dddd`	`ffff`	`ffff`	`ffff`	`ffff`	`BD01`
Description:	Compute the 2’s complement of the contents of the file register and place the result in the destination designated by D. If the optional Wnd is specified, D=0 and store result in Wnd; otherwise, D=1 and store result in the file register. The ‘L’ and ‘B’ bits select operation data width. The ‘D’ bit selects the destination. The ‘f’ bits select the address of the file register. The ‘d’ bits select the Working register.
I-Words:	1
Cycles:	1


Example 1:		`NEG.B 0x880, WREG ; Negate (0x880) (Byte mode)` `; Store result to WREG`
		Before Instruction					After Instruction
WREG (W0)			9080	WREG (W0)				90AB
Data 0880			2355		Data 0880			2355
	SR		0000			SR		0008	(N = 1)


Example 2:		`NEG 0x1200 ; Negate (0x1200) (Word mode)`
		Before Instruction				After Instruction
Data 1200			8923	Data 1200			76DD
	SR		0000		SR		0000


NEOP		None Executable No Operation
Syntax:	{label:}	NEOP







Operands:	None
Operation:	No Operation
Status Affected:	None
Encoding:	`0000`	`0000`	`UUUU`	`UUUU`
Description:	No Operation is performed. This instruction will also consume no execution time. It can be regarded as a means to pad a 16-bit instruction (to use a 32-bit word) when the instruction cannot be paired with another 16-bit instruction (to maintain alignment).
I-Words:	0.5
Cycles:	0


NOP		No Operation
Syntax:	{label:}	NOP







Operands:	None
Operation:	No Operation
Status Affected:	None
Encoding:	`0000`	`0001`	`UUUU`	`UUUU`
Description:	No Operation is performed.
I-Words:	1
Cycles:	1


	`NOP ; execute no operation`
	Before Instruction			After Instruction
PC		00 1092	PC		00 1094
SR		0000	SR		0000


	`NOP ; execute no operation`
	Before Instruction			After Instruction
PC		00 08AE	PC		00 08B0
SR		0000	SR		0000


NOPR		No Operation (32-bit)
Syntax:	{label:}	NOPR







Operands:	None
Operation:	No Operation
Status Affected:	None
Encoding:	`1111`	`111U`	`UUUU`	`UUUU`	`UUUU`	`UUUU`	`UUUU`	`UU11`
Description:	No Operation is performed.
I-Words:	1
Cycles:	1


	`NOPR ; execute no operation`
	Before Instruction			After Instruction
PC		00 2430	PC		00 2432
SR		0000	SR		0000


	`NOPR ; execute no operation`
	Before Instruction			After Instruction
PC		00 1466	PC		00 1468
SR		0000	SR		0000


NORM		Normalize Accumulator
Syntax:	{label:}	NORM{.w} A,		Wd
		NORM.l	B,	[Wd]
				[Wd++]
				[Wd--]
				[++Wd]
				[--Wd]
				[Wd+Wb]



Operands:	Wd ∈ [W0 ... W15], Wb ∈ [W0 ... W15]
Operation:	refer to text
Status Affected:	OA or OB, N, Z
Encoding:	`1100`	`10AL`	`wwww`	`dddd`	`UUUq`	`qqUU`	`UUUU`	`1111`
Description:	Normalize the contents of the target accumulator. If the accumulator contains an overflowed value, the contents of the accumulator are shifted right by the minimum number of bits required to remove the overflow. If the accumulator does not contain an overflowed value, the contents of the accumulator are shifted left by the minimum number of bits required to produce the largest fractional data value without an overflow. If it is not possible to normalize the target accumulator (i.e., it is already normalized, or it is all 0’s or all 1’s) Wd is cleared and the Z bit is set (and the N bit is cleared). The target accumulator is unaffected. If it is possible to normalize the target accumulator, the exponent (shift value) required to normalize the target accumulator is written into Wd. A positive result indicates that a right shift of the accumulator was required for normalization. A negative result indicates that a left shift of the accumulator was required for normalization. The N bit is set to reflect the sign of the result and the Z bit is cleared.   The ‘L’ bit selects word or long word Wd destination. The ‘A’ bit specifies the destination accumulator. The ‘d’ bits select the destination register. The ‘q’ bits select the destination addressing mode. The ‘w’ bits define the offset Wb. Note: OA or OB status bits are set based on the content of the target accumulator. Consequently, because NORM removes any overflow, OA or OB will always be cleared.  SA/SB are ‘sticky’ so will remain set if set prior to execution of the NORM, but they can never be affected by this instruction.
I-Words:	1
Cycles:	1


POP		Pop Top of Return Stack
Syntax:	{label:}	POP.I	f







Operands:	f ∈ [0 ... 1MB]
Operation:	(W15) - 4 → W15; (TOS) → (f,2’b00)
Status Affected:	None
Encoding:	`1011`	`1101`	`ffff`	`ffff`	`ffff`	`ffff`	`ffff`	`UU01`
Description:	The Stack Pointer (W15) is pre-decremented and Top-of-Stack (TOS) value is pulled off the stack and written to the file register. The ‘f’ bits select the address of the file register. Note: This instruction operates in Long Word mode only. The LS 2-bits of the file address will therefore always be 2’b00. Accessible file address space is 1MB.
I-Words:	1
Cycles:	1


POP		Pop Working (W) Register
Syntax:	{label:}	POP.l	Wnd



Operands:	Wnd ∈ [W0 ... W15]
Operation:	POP.l ^1,2: (W15) - 4 → W15; (TOS) → Wnd
Status Affected:	None
Encoding:	`0001`	`110L`	`dddd`	`ssss`
Description:	Move the top of a LIFO stack data structure (or data memory) to the destination Working register, Wnd. Use of the system Stack Pointer ([--W15]) is implied for POP.l. The ‘L’ bit selects operation data width. The ‘s’ bits select the Working Source register. The ‘d’ bits select the Working Destination register.
I-Words:	0.5
Cycles:	1

Note:

1. This instruction operates in Long Word mode only. The LS 2-bits of the file address will therefore always be 2’b00.
Accessible file address space is 1MB.


PUSH		Push Top of Return Stack (TOS)
Syntax:	{label:}	PUSH.I	f







Operands:	f ∈ [0 ... 1MB]
Operation:	(f) → (TOS); (W15)+4 → W15
Status Affected:	None
Encoding:	`1011`	`1111`	`ffff`	`ffff`	`ffff`	`ffff`	`ffff`	`UU01`
Description:	The file register contents are written to the Top of Stack (TOS) location. The Stack Pointer (W15) is then incremented. The ‘f’ bits select the address of the file register. Note: This instruction operates in Long Word mode only. The LS 2-bits of the file address will therefore always be 2’b00. Accessible file address space is 1MB.
I-Words:	1
Cycles:	1


Example 1:	`PUSH 0x2004 ; Push (0x2004) to TOS`
		Before Instruction				After Instruction
W15			0B00	W15			0B02
Data 0B00			791C	Data 0B00			D400
Data 2004			D400	Data 2004			D400
	SR		0000		SR		0000


Example 2:	`PUSH 0xC0E ; Push (0xC0E) to TOS`
		Before Instruction				After Instruction
W15			0920	W15			0922
Data 0920			0000	Data 0920			67AA
Data 0C0E			67AA	Data 2004			67AA
	SR		0000		SR		0000


PUSH		Push Working (W) Register
Syntax:	{label:}	PUSH.l	Wns



Operands:	Wns ∈ [W0 ... W15];
Operation:	PUSH.l ^1,2: Wns → (TOS); (W15)+4 → W15
Status Affected:	None
Encoding:	`0001`	`111L`	`dddd`	`ssss`
Description:	Move the contents of the source Working register, Wns, to the top of a LIFO stack data structure (or data memory). Use of the system Stack Pointer ([W15++]) is implied for PUSH.l. The ‘L’ bit selects operation data width. The ‘s’ bits select the Working Source register. The ‘d’ bits select the Working Destination register.
I-Words:	0.5
Cycles:	1

Note:

PUSH.l Wns is functionally equivalent to MOV.l Wns, [W15++].
In order to preserve system stack Long Word alignment, the PUSH mnemonic only supports Long Word mode, and even the MOV.w mnemonic does not permit use of W15 as destination.


PWRSAV		Enter Power Saving Mode
Syntax:	{label:}	PWRSAV	lit1







Operands:	lit1 ∈ [0 ... 1]
Operation:	0 → Sleep-mode WDT 1 → WDTO 0 → SLEEP 0 → IDLE Enter either IDLE or SLEEP mode
Status Affected:	SLEEP, IDLE
Encoding:	`0111`	`001U`	`UUUk`	`0111`
Description:	If lit1 = 0, device is placed in SLEEP mode. If lit1 = 1, device is placed in IDLE mode. The Sleep-mode WDT is reset. The SLEEP and IDLE status bits (located within the RCON register) are cleared. If SLEEP mode is selected, the device is shut down. The oscillator source is stopped. If IDLE is selected, the CPU is shut down, but the peripherals continue to operate. The processor will exit from SLEEP or IDLE mode through an interrupt or a reset or a Watchdog Time-Out. If exiting from IDLE mode, the clock source is reapplied to CPU. If exiting from SLEEP mode, the clock source is restarted. If waking from SLEEP mode : 1 → SLEEP (in RCON register) If waking from IDLE mode : 1 → IDLE (in RCON register) If awakened by a WDT timeout: 1 → WDTO The ‘k’ bit select the Power Saving mode.
I-Words:	0.5
Cycles:	2


Example 1:	`PWRSAV #0 ; Enter SLEEP mode`
		Before Instruction					After Instruction
	SR		0040	(IPL = 2)			SR	0040	(IPL = 2)


Example 2:	`PWRSAV #1 ; Enter IDLE mode`
		Before Instruction					After Instruction
	SR		0020	(IPL = 1)			SR	0020	(IPL = 1)


RCALL		Relative Call
Syntax:	{label:}	RCALL	Label







Operands:	Label is resolved by the linker to a signed word offset (slit20)
Operation:	(PC) + 4 → PC, (8’b0, PC[23:2]) → TOS[31:2]; 2’b00 → TOS[1:0], (W15) + 4 → W15, PC+ 2*slit20 → PC; NOP → Instruction Register
Status Affected:	None
Encoding:	`1101`	`010U`	`nnnn`	`nnnn`	`nnnn`	`nnnn`	`nnnn`	`0010`
Description:	Subroutine call with a forward or backward branch address range of 1MB to either a 32-bit or 16-bit instruction. The long word aligned return address (PC+4) is pushed onto the system stack. The 2’s complement byte offset value ‘2slit20’ (the PC offset) is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+4) + 2slit20. The ‘n’ bits are a signed literal that specifies the number of PS words to branch from (PC+4).
I-Words:	1
Cycles:	1


Example 1:		`012004 RCALL _Task1` `012006 ADD W0, W1, W2` `. ...` `. ...` `012458 _Task1: SUB W0, W2, W3` `01245A ...`
		Before Instruction				After Instruction
	PC		01 2004		PC		01 2458
W15			0810	W15			0814
Data 0810			FFFF	Data 0810			2006
Data 0812			FFFF	Data 0812			0001
	SR		0000		SR		0000


Example 2:		`00620E RCALL _Init006210 MOV W0, [W4++]` `. ...` `. ...007000 _Init: CLR W2007002 ...`
		Before Instruction				After Instruction
	PC		00 620E		PC		00 7000
W15			0C50	W15			0C54
Data 0C50			FFFF	Data 0C50			6210
Data 0C52			FFFF	Data 0C52			0000
	SR		0000		SR		0000


RCALL		Computed Call
Syntax:	{label:}	RCALL	Wns







Operands:	Wns ∈ [W0 ... W15]
Operation:	(PC) + 4 → PC, (8’b0, PC[23:0]) → TOS[31:0], (W15) + 4 → W15, (PC) + 2*Wns[19:0] → PC; NOP → Instruction Register
Status Affected:	None
Encoding:	`1101`	`011U`	`UUUU`	`ssss`	`UUUU`	`UUUU`	`UUUU`	`0110`
Description:	Computed subroutine call with a forward or backward branch address range of 1MB to any size of instruction. The long word aligned return address (PC+4) is pushed onto the system stack. The signed value in Wns[19:0] represents the PS (16-bit) word offset from the current PC. This value is multiplied by 2 to create a byte address which is then added to the contents of the PC to form the target address. Wn must therefore contain a signed value that specifies the number of PS words to offset from (PC+4) for the call. RCALLW is a two-cycle instruction. The ‘s’ bits specify the source register. Note: If Wns[31:19] is not all 0’s or all 1’s, an address error trap will be initiated.
I-Words:	1
Cycles:	2 Note: The call target instruction fetch is not executed if an exception is pending, making effective instruction execution time one cycle.


REPEAT		Repeat next instruction, literal count
Syntax:	{label:}	REPEAT	lit20







Operands:	lit20 ∈ [0 ... 1048575]
Operation:	(12’h000, lit20) → RCOUNT[31:0] (Loop Count Register) (PC) + 4 → PC 1 → RA (Enable Code Looping)
Status Affected:	RA (if lit20 > 0)
Encoding:	`1101`	`010U`	`kkkk`	`kkkk`	`kkkk`	`kkkk`	`kkkk`	`0110`
Description:	The instruction immediately following the REPEAT instruction is executed (lit20+1) times. The repeated instruction is held in the instruction register for all iterations and so is fetched only once (during the REPEAT instruction, as would be expected). The last iteration of the repeated instruction fetches the next instruction. The repeat count is decremented during each iteration. When it equals zero (during the penultimate loop), PC increment and instruction fetch is re-enabled (RA=0) allowing the final iteration to fetch the next instruction and normal execution continues. The repeated instruction can be interrupted before any iteration by any interrupt. Note that the user must save and restore RCOUNT to support nested repeats (e.g., from within the interrupt service routine). The ‘k’ bits are an unsigned literal that specifies the loop count. Note: If lit20 = 0, RA is not set and the subsequent instruction executes as normal (equivalent to a loop count of one).
I-Words:	1
Cycles:	1


REPEAT		Repeat next instruction, short literal count
Syntax:	{label:}	REPEAT	lit5







Operands:	lit5 ∈ [0 ... 31]
Operation:	(27’h000000, lit5) → RCOUNT[31:0] (Loop Count Register) (PC) + 2 → PC 1 → RA (Enable Code Looping)
Status Affected:	RA (if lit5 > 0)
Encoding:	`0111`	`001k`	`kkkk`	`1111`
Description:	The instruction immediately following the REPEAT instruction is executed (lit5+1) times. If lit5 > 31, assemble as REPEAT instruction. The repeated instruction is held in the instruction register for all iterations and so is fetched only once (during the REPEAT instruction, as would be expected). The last iteration of the repeated instruction fetches the next instruction. The repeat count is decremented during each iteration. When it equals zero (during the penultimate loop), PC increment and instruction fetch is re-enabled (RA=0) allowing the final iteration to fetch the next instruction and normal execution continues. The repeated instruction can be interrupted before any iteration by any interrupt. Note that the user must save and restore RCOUNT to support nested repeats (e.g., from within the interrupt service routine). The ‘k’ bits are an unsigned literal that specifies the loop count. Note: If lit5 = 0, RA is not set and the subsequent instruction executes as normal (equivalent to a loop count of one)
I-Words:	0.5
Cycles:	1


REPEAT		Repeat next instruction, variable count
Syntax:	{label:}	REPEAT	Wn







Operands:	Wn ∈ [W0 ... W15]
Operation:	(Wn[31:0]) → RCOUNT[31:0] (Loop Count Register) (PC) + 2 → PC 1 → RA (Enable Code Looping)
Status Affected:	RA (if (Wn) > 0)
Encoding:	`1101`	`100U`	`UUUU`	`ssss`	`UUUU`	`UUUU`	`UUUU`	`U010`
Description:	The instruction immediately following the REPEAT instruction is executed (Wn)+1 times. The repeated instruction is held in the instruction register for all iterations and so is fetched only once (during the REPEAT instruction, as would be expected). The last iteration of the repeated instruction fetches the next instruction. The repeat count is decremented during each iteration. When it equals zero (during the penultimate loop), PC increment and instruction fetch is re-enabled (RA=0) allowing the final iteration to fetch the next instruction and normal execution continues. The repeated instruction can be interrupted before any iteration by any interrupt. Note that the user must save and restore RCOUNT to support nested repeats (e.g., from within the interrupt service routine). The ‘s’ bits specify the Wn register that contains the loop count Note: If Wn = 0, RA is not set and the subsequent instruction executes as normal (equivalent to a loop count of one).
I-Words:	1
Cycles:	1


RESET		Reset
Syntax:	{label:}	RESET







Operands:	None
Operation:	Force all registers and flag bits that are affected by an MCLR reset to their Reset condition.
Status Affected:	None
Encoding:	`1111`	`101U`	`UUUU`	`UUUU`	`UUUU`	`UUUU`	`UUUU`	`0011`
Description:	This instruction provides a means to execute a software reset.
I-Words:	1
Cycles:	1


Example 1:		`00202A RESET ; Execute software RESET on dsPIC33A`
		Before Instruction					After Instruction
	PC		00 202A			PC		00 0000
W0			8901		W0			0000
W1			08BB		W1			0000
W2			B87A		W2			0000
W3			872F		W3			0000
W4			C98A		W4			0000
W5			AAD4		W5			0000
W6			981E		W6			0000
W7			1809		W7			0000
W8			C341		W8			0000
W9			90F4		W9			0000
W10			F409		W10			0000
W11			1700		W11			0000
W12			1008		W12			0000
W13			6556		W13			0000
W14			231D		W14			0000
W15			1704		W15			0800
SPLIM			1800		SPLIM			0000
TBLPAG			007F		TBLPAG			0000
PSVPAG			0001		PSVPAG			0000
CORCON			00F0		CORCON			0020	(SATDW = 1)
RCON			0000		RCON			0040	(SWR = 1)
	SR		0021	(IPL, C = 1)		SR		0000


RETFIE		Return from Interrupt
Syntax:	{label:}	RETFIE




Operands:	None
Operation:	(W15) - 4 → W15 TOS[23:1] → (PC[23:1]), (W15) - 4 → W15 TOS[15:0] → (SR[31:0]), 1’b0 → PC[0] NOP → Instruction Register
Status Affected:	OA, OB, SA, SB, (OAB), (SAB), IPL[3:0], RA, N, OV, Z, C
Encoding:	`0111`	`001U`	`UUUU`	`0000`
Description:	Return from interrupt service routine to either a 32-bit or 16-bit instruction. The stack is popped and the Top of Stack (TOS) is loaded into PC[23:1] (PC[0] is always clear).The stack is popped again and the Top of Stack (TOS) is loaded into the SR. In addition, this instruction will also manage hardware context switching (IPL-based). Note: OAB and SAB will reflect the returned state of OA/OB and SA/SB respectively.
I-Words:	0.5
Cycles:	4 Note: Return PC instruction fetch is not executed if an exception is pending, making effective instruction execution time (for latency) one cycle.


Example 1:		`000A26 RETFIE ; Return from ISR`
		Before Instruction				After Instruction
	PC		00 0A26		PC		01 0230
W15			0834	W15			0830
Data 0830			0230	Data 0830			0230
Data 0832			8101	Data 0832			8101
CORCON			0001	CORCON			0001
	SR		0000		SR		0081	(IPL = 4, C = 1)


Example 2:		`008050 RETFIE ; Return from ISR`
		Before Instruction				After Instruction
	PC		00 8050		PC		00 7008
W15			0926	W15			0922
Data 0922			7008	Data 0922			7008
Data 0924			0300	Data 0924			0300
CORCON			0000	CORCON			0000
	SR		0000		SR		0003	(Z, C = 1)


RETLW		Return with Literal in Wd
Syntax:	{label:}	RETLW.b	lit16,	Wnd
		RETLW.bz
		RETLW{.w}
		RETLW.l

Operands:	Wnd ∈ [W0 ... W14]; lit16 ∈ [0 ... 65535]
Operation:	(W15) - 4 → W15 TOS[23:1] → (PC[23:1]), 1’b0 → PC[0] Byte mode: lit16[7:0] → Wnd[7:0] Extended Byte mode: 24’b0, lit16[7:0] → Wnd Word or Long Word mode: 16’b0, lit16 → Wnd NOP → Instruction Register
Status Affected:	None
Encoding:	`1100`	`110L`	`dddd`	`kkkk`	`kkkk`	`kkkk`	`kkkk`	`BU10`
Description:	Return with a literal value in Wnd. When operating in Long Word, Word or Extended Byte mode, the literal is zero-extended to 32-bits before being written into Wnd. When operating in Byte mode, the literal is loaded into the LSb of Wnd, leaving the MSb of Wnd unchanged. The ‘L’ and ‘B’ bits select operation data width. The ‘d’ bits select the destination register. The ‘k’ bits define the literal. Note: W15 is excluded from being a valid destination for the return literal value. Word and Long Word operating modes are equivalent. Return PC instruction fetch is not executed if an exception is pending, making effective instruction execution time (for latency) one cycle.
I-Words:	1
Cycles:	3 (refer to note 3)


RETURN		Return
Syntax:	{label:}	RETURN







Operands:	None
Operation:	(W15) - 4 → W15 TOS[23:1] → (PC[23:1]) 1’b0 → PC[0] NOP → Instruction Register
Status Affected:	None
Encoding:	`0111`	`001U`	`UUUU`	`0001`
Description:	Return from subroutine to either a 32-bit or 16-bit instruction. The stack is popped and the Top-of-Stack (TOS) is loaded into PC[23:0]. PC[0] is always clear.
I-Words:	0.5
Cycles:	3 Note: Return PC instruction fetch is not executed if an exception is pending, making effective instruction execution time (for latency) 1 cycle.


Example 1:		`001A06 RETURN ; Return from subroutine`
		Before Instruction				After Instruction
	PC		00 1A06		PC		01 0004
W15			1248	W15			1244
Data 1244			0004	Data 1244			0004
Data 1246			0001	Data 1246			0001
	SR		0000		SR		0000


Example 2:		`005404 RETURN ; Return from subroutine`
		Before Instruction				After Instruction
	PC		00 5404		PC		00 0966
W15			090A	W15			0906
Data 0906			0966	Data 0906			0966
Data 0908			0000	Data 0908			0000
	SR		0000		SR		0000


RLC		Rotate Left Ws through Carry
Syntax:	{label:}	RLC.b	Ws,	Wd
		RLC.bz	[Ws],	[Wd]
		RLC{.w}	[Ws++],	[Wd++]
		RLC.l	[Ws--],	[Wd--]
			[++Ws],	[++Wd]
			[--Ws],	[--Wd]


Operands:	Ws ∈ [W0 ... W15]; Wd ∈ [W0 ... W15]
Operation:	For Byte operation: (C) → Wd[0], (Ws[6:0]) → Wd[7:1], (Ws<7>) → C For Word operation: (C) → Wd[0], (Ws[14:0]) → Wd[15:1], (Ws[15]) → C For Long Word operation: (C) → Wd[0], (Ws[30:0]) → Wd[31:1], (Ws[31]) → C
Status Affected:	C, N, Z
Encoding:	`S011`	`000L`	`dddd`	`ssss`	`pppq`	`qqUU`	`UUUU`	`BU00`
Description:	Rotate the contents of the source register Ws one bit to the left through the carry flag and place the result in the destination register Wd. In all cases, N and Z are set based on an evaluation of the result using the data size of the operation. The ‘S’ bit selects instruction size. The ‘L’ and ‘B’ bits select operation data width. The ‘s’ bits select the source register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode.
I-Words:	1 or 0.5
Cycles:	1


Example 1		RLC.B W0, W3					;Rotate Left w/C (W0) (Byte mode) ;Store the result in W3
		Before Instruction				After Instruction
W0			9976	W0			9976
	W3		5879		W3		58ED
	SR		0001	(C = 1)	SR		0009	(N = 1)
Example 2		[W2++],[W8]					;Rotate Left w/C [W2] (Word mode) ;Post-increment W2 ;Store result in [W8]
		Before Instruction				After Instruction
W2			2008	W2			200A
	W8		094E		W8		094E
	Data 094E		3689		Data 094E		8082	(N = 1)
	Data 2008		C041		Data 2008		C041
	SR		0001	(C = 1)	SR		0009	(N, C = 1)


RLC		Rotate Left f through Carry
Syntax:	{label:}	RLC.b	f	{,Wnd}	{,WREG}
		RLC.bz
		RLC{.w}
		RLC.l




Operands:	f ∈ [0 ... 64KB]; Wnd ∈ [W0 ... W14]
Operation:	For Byte operation: (C) → Dest[0], (f[6:0]) → Dest[7:1], (f<7>) → C For Word operation: (C) → Dest[0], (f[14:0]) → Dest[15:1], (f[15]) → C For Long Word operation: (C) → Dest[0], (f[30:0]) → Dest[31:1], (f[31]) → C
Status Affected:	C, N, Z
Encoding:	`1011`	`000L`	`dddd`	`ffff`	`ffff`	`ffff`	`ffff`	`BD01`
Description:	Rotate the contents of the file register f one bit to the left through the carry flag and place the result in the destination designated by D. If the optional Wnd is specified, D=0 and store result in Wnd; otherwise, D=1 and store result in the file register. The ‘L’ and ‘B’ bits select operation data width. The ‘D’ bit selects the destination. The ‘f’ bits select the address of the file register. The ‘d’ bits select the Working register.
I-Words:	1
Cycles:	1


Example 1		RLC.B 0x1233					; Rotate Left w/ C (0x1233) (Byte mode)
		Before Instruction				After Instruction
Data 1232			E807	Data 1232			D007
	SR		0000		SR		0009	(N, C = 1)
Example 2		RLC 0x820, WREG					; Rotate Left w/ C (0x820) (Word mode) ; Store result in WREG
		Before Instruction				After Instruction
WREG (W0)			5601	WREG (W0)			42DD
	Data 0820		216E		Data 0820		216E
	SR		0001	(C = 1)	SR		0000	(C = 0)


RLNC		Rotate Left Ws (No Carry)
Syntax:	{label:}	RLNC.b	Ws,	Wd
		RLNC.bz	[Ws],	[Wd]
		RLNC{.w}	[Ws++],	[Wd++]
		RLNC.l	[Ws--],	[Wd--]
			[++Ws],	[++Wd]
			[--Ws],	[--Wd]


Operands:	Ws ∈ [W0 ... W15]; Wd ∈ [W0 ... W15]
Operation:	For Byte operation: (Ws[6:0]) → Wd[7:1], (Ws<7>) → Wd[0] For Word operation: (Ws[14:0]) → Wd[15:1], (Ws[15]) → Wd[0]  For Long Word operation: (Ws[30:0]) → Wd[31:1], (Ws[31]) → Wd[0]
Status Affected:	N, Z
Encoding:	`S011`	`001L`	`dddd`	`ssss`	`pppq`	`qqUU`	`UUUU`	`BU00`
Description:	Rotate the contents of the source register Ws one bit to the left and place the result in the destination register Wd. The Carry Flag bit is not affected. The ‘S’ bit selects instruction size. The ‘L’ and ‘B’ bits select operation data width. The ‘s’ bits select the source register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode.
I-Words:	1 or 0.5
Cycles:	1


Example 1		RLNC.B W0, W3					; Rotate Left (W0) (Byte mode) ; Store the result in W3
		Before Instruction				After Instruction
W0			9976	W0			9976
	W3		5879		W3		58EC
	SR		0001		SR		0009	(N, C = 1)


Example 2		RLNC [W2++], [W8]					; Rotate Left [W2] (Word mode) ; Post-increment W2 ; Store result in [W8]
		Before Instruction				After Instruction
W2			2008	W2			200A
	W8		094E		W8		094E
	Data 094E		3689		Data 094E		8083
	Data 2008		C041		Data 2008		C041
	SR		0001	(C = 1)	SR		0009	(N, C = 1)


RLNC		Rotate Left f (No Carry)
Syntax:	{label:}	RLNC.b	f	{,Wnd}	{,WREG}
		RLNC.bz
		RLNC{.w}
		RLNC.l




Operands:	f ∈ [0 ... 64KB]; Wnd ∈ [W0 ... W14]
Operation:	For Byte operation: (f[6:0]) → Dest[7:1], (f<7>) → Dest[0] For Word operation: (f[14:0]) → Dest[15:1], (f[15]) → Dest[0] For Long Word operation: (f[30:0]) → Dest[31:1], (f[31]) → Dest[0]
Status Affected:	N, Z
Encoding:	`1011`	`001L`	`dddd`	`ffff`	`ffff`	`ffff`	`ffff`	`BD01`
Description:	Rotate the contents of the file register f one bit to the left and place the result in the destination designated by D. If the optional Wnd is specified, D=0 and store result in Wnd; otherwise, D=1 and store result in the file register. The Carry Flag bit is not affected. The ‘L’ and ‘B’ bits select operation data width. The ‘D’ bit selects the destination. The ‘f’ bits select the address of the file register. The ‘d’ bits select the Working register.
I-Words:	1
Cycles:	1


Example 1		RLNC.B 0x1233					; Rotate Left (0x1233) (Byte mode)
		Before Instruction				After Instruction
Data 1232			E807	Data 1233			D107
	SR		0000		SR		0008	(N = 1)


Example 2		RLNC 0x820, WREG					; Rotate Left (0x820) (Word mode) ; Store result in WREG
		Before Instruction				After Instruction
WREG (W0)			5601	WREG (W0)			42DC
	Data 0820		216E		Data 0820		216E
	SR		0001	(C = 1)	SR		0000	(C = 0)


RRC		Rotate Right Ws through Carry
Syntax:	{label:}	RRC.b	Ws,	Wd
		RRC.bz	[Ws],	[Wd]
		RRC{.w}	[Ws++],	[Wd++]
		RRC.l	[Ws--],	[Wd--]
			[++Ws],	[++Wd]
			[--Ws],	[--Wd]


Operands:	Ws ∈ [W0 ... W15]; Wd ∈ [W0 ... W15]
Operation:	For Byte operation: (C) → Wd<7>, (Ws[7:1]) → Wd[6:0], (Ws[0]) → C For Word operation: (C) → Wd[15], (Ws[15:1]) → Wd[14:0], (Ws[0]) → C For Long Word operation: (C) → Wd[31], (Ws[31:1]) → Wd[30:0], (Ws[0]) → C
Status Affected:	C, N, Z
Encoding:	`S011`	`010L`	`dddd`	`ssss`	`pppq`	`qqUU`	`UUUU`	`BU00`
Description:	Rotate the contents of the source register Ws one bit to the right through the carry flag and place the result in the destination register Wd. The ‘S’ bit selects instruction size. The ‘L’ and ‘B’ bits select operation data width. The ‘s’ bits select the source register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode.
I-Words:	1 or 0.5
Cycles:	1


Example 1:	RRC.B W0, W3							; Rotate Right w/ C (W0) (Byte mode) ; Store the result in W3
		Before Instruction				After Instruction
W0			9976		W0		9976
W3			5879		W3		58BB
	SR		0001	(C = 1)		SR	0008	(N = 1)


Example 2:	`RRC [W2++], [W8]`							; Rotate Right w/ C [W2] (Word mode) ; Post-increment W2 ; Store result in [W8]
		Before Instruction				After Instruction
W2			2008	W2			200A
W8			094E	W8			094E
Data 094E			3689		Data 094E		E020
Data 2008			C041		Data 2008		C041
	SR		0001	(C = 1)		SR	0009	(N, C = 1)


RRC		Rotate Right f through Carry
Syntax:	{label:}	RRC.b	f	{,Wnd}	{,WREG}
		RRC.bz
		RRC{.w}
		RRC.l




Operands:	f ∈ [0 ... 64KB]; Wnd ∈ [W0 ... W14]
Operation:	For Byte operation: (C) → Dest[7], (f[7:1]) → Dest[6:0], (f[0]) → C For Word operation: (C) → Dest[15], (f[15:1]) → Dest[14:0], (f[0]) → C For Long Word operation: (C) → Dest[31], (f[31:1]) → Dest[30:0], (f[0]) → C
Status Affected:	C, N, Z
Encoding:	`1011`	`010L`	`dddd`	`ffff`	`ffff`	`ffff`	`ffff`	`BD01`
Description:	Rotate the contents of the file register f one bit to the left through the carry flag and place the result in the destination designated by D. If the optional Wnd is specified, D=0 and store result in Wnd; otherwise, D=1 and store result in the file register. The ‘L’ and ‘B’ bits select operation data width. The ‘D’ bit selects the destination. The ‘f’ bits select the address of the file register. The ‘d’ bits select the Working register.
I-Words:	1
Cycles:	1


Example 1		RRC.B 0x1233					;Rotate Right w/C (0x1233) (Byte mode)
		Before Instruction				After Instruction
Data 1232			E807	Data 1232			7407
	SR		0000		SR		0000


Example 2:	RRC 0x820, WREG						; Rotate Right w/C (0x820) (Word mode) ; Store result in WREG
		Before Instruction				After Instruction
WREG (W0)			5601	WREG (W0)			90B7
Data 0820			216E		Data 0820		216E
	SR		0001	(C = 1)		SR	0008	(N = 1)


RRNC		Rotate Right Ws (No Carry)
Syntax:	{label:}	RRNC.b	Ws,	Wd
		RRNC.bz	[Ws],	[Wd]
		RRNC{.w} [Ws++],		[Wd++]
		RRNC.l	[Ws--],	[Wd--]
			[++Ws],	[++Wd]
			[--Ws],	[--Wd]


Operands:	Ws ∈ [W0 ... W15]; Wd ∈ [W0 ... W15]
Operation:	For Byte operation: (Ws[7:1]) → Wd[6:0], (Ws[0]) → Wd<7> For Word operation: (Ws[15:1]) → Wd[14:0], (Ws[0]) → Wd[15] For Long Word operation: (Ws[31:1]) → Wd[30:0], (Ws[0]) → Wd[31]
Status Affected:	N, Z
Encoding:	`S011`	`011L`	`dddd`	`ssss`	`pppq`	`qqUU`	`UUUU`	`BU00`
Description:	Rotate the contents of the source register Ws one bit to the right and place the result in the destination register Wd. The Carry Flag bit is not affected. The ‘S’ bit selects instruction size. The ‘L’ and ‘B’ bits select operation data width. The ‘s’ bits select the source register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode.
I-Words:	1 or 0.5
Cycles:	1


Example 1		RRNC.B W0, W3					; Rotate Right (W0) (Byte mode) ; Store the result in W3
		Before Instruction				After Instruction
W0			9976	W0			9976
W3			5879	W3			583B
	SR		0001	(C = 1)	SR		0001	(C = 1)


Example 2:	RRNC [W2++], [W8]						; Rotate Right [W2] (Word mode) ; Post-increment W2 ; Store result in [W8]
		Before Instruction				After Instruction
W2			2008	W2			200A
W8			094E		W8		094E
Data 094E			3689		Data 094E		E020
Data 2008			C041		Data 2008		C041
	SR		0000	(C = 1)		SR	0008	(N = 1)


RRNC		Rotate Right f (No Carry)
Syntax:	{label:}	RRNC.b	f	{,Wnd}	{,WREG}
		RRNC.bz
		RRNC{.w}
		RRNC.l




Operands:	f ∈ [0 ... 64KB]; Wnd ∈ [W0 ... W14]
Operation:	For Byte operation: (f[7:1]) → Dest[6:0], (f[0]) → Dest[7] For Word operation: (f[15:1]) → Dest[14:0], (f[0]) → Dest[15] For Long Word operation: (f[31:1]) → Dest[30:0], (f[0]) → Dest[31]
Status Affected:	N, Z
Encoding:	`1011`	`011L`	`dddd`	`ffff`	`ffff`	`ffff`	`ffff`	`BD01`
Description:	Rotate the contents of the file register f one bit to the right, and place the result in the destination designated by D. If the optional Wnd is specified, D=0 and store result in Wnd; otherwise, D=1 and store result in the file register. The Carry Flag bit is not affected. The ‘L’ and ‘B’ bits select operation data width. The ‘D’ bit selects the destination. The ‘f’ bits select the address of the file register. The ‘s’ bits select the Working register.
I-Words:	1
Cycles:	1


Example 1	RRNC.B 0x1233				; Rotate Right (0x1233) (Byte mode)
	Before Instruction			After Instruction
Data 1232		E807	Data 1232		7407
SR		0000	SR		0000


Example 2:	RRNC 0x820, WREG						; Rotate Right (0x820) (Word mode) ; Store result in WREG
		Before Instruction				After Instruction
WREG (W0)			5601	WREG (W0)			10B7
Data 0820			216E		Data 0820		216E
	SR		0001	(C = 1)		SR	0001	(C = 1)


SAC		Store Accumulator
Syntax:	{label:}	SAC{.w}	A,	{ Slit6, }	Wd
		SAC.l	B,		[Wd]
					[Wd++]
					[Wd--]
					[--Wd]
					[++Wd]
					[Wd+Wb]

Operands:	Slit6 ∈ [-32 ... +31]; Wd ∈ [W0 ... W15] (see note 4); Wb ∈ [W0 ... W15]
Operation:	For Long Word operation: Shift_Slit6(ACC) (ACC[63:32]) → Wd[31:0] For Word operation: Shift_Slit6(ACC) (ACC[63:48]) → Wd[15:0] (see note 3)
Status Affected:	None
Encoding:	`1100`	`01AL`	`wwww`	`dddd`	`UUUq`	`qqkk`	`kkkk`	`0011`
Description:	Read then optionally shift accumulator value, then store the truncated result to the destination Effective Address. Any shift will apply only to data read from the accumulator, so will not modify the accumulator contents. The shift value is sourced from a signed literal value. After the shift, a word operation (SAC{.w}) assumes that the value is a Q1.15 signed fraction. Accordingly, the post-shift result [63:48] is then written to the Effective Address. After the shift, a long word operation (SAC.l) assumes that the value is a Q1.31 signed fraction. Accordingly, the post-shift result [63:32] is then written to the Effective Address. The ‘L’ bit selects word or long word operation. The ‘A’ bit specifies the source accumulator. The ‘d’ bits specify the destination register Wd. The ‘q’ bits select the destination addressing mode. The ‘w’ bits specify the offset register Wb. The ‘k’ bits encode the optional operand Slit6 which determines the amount of the accumulator shift. If operand Slit6 is absent, set literal to all 0’s. Note: Positive values of operand Slit6 represent arithmetic shift right. Negative values of operand Slit6 represent shift left. When the destination is register direct (W-reg), the result is either zero extended (CORCON.US = 1) or sign extended (CORCON.US = 0) to 32-bits. Register direct destination W15 not permitted.
I-Words:	1
Cycles:	1


Example 1:	SAC A, #4, W5			; Right shift ACCA by 4 ; Store result to W5 ; CORCON = 0x0010 (SATDW = 1)
		Before Instruction		After Instruction
	W5	B900	W5	0120
ACCA		00 120F FF00	ACCA	00 120F FF00
CORCON		0010	CORCON	0010
	SR	0000	SR	0000


Example 2:	SAC B, #-4, [W5++]			; Left shift ACCB by 4 ; Store result to [W5], Post-increment W5 ; CORCON = 0x0010 (SATDW = 1)
		Before Instruction		After Instruction
	W5	2000	W5	2002
ACCB		FF C891 8F4C	ACCB	FF C891 1F4C
Data 2000		5BBE	Data 2000	8000
CORCON		0010	CORCON	0010
	SR	0000	SR	0000


SE		Sign Extend Ws
Syntax:	{label:}	SE.b	Ws,	Wnd
		SE.w	[Ws],
			[Ws++],
			[Ws--],
			[++Ws],
			[--Ws],
			[Ws+Wb],

Operands:	Ws ∈ [W0 ... W15]; Wb ∈ [W0 ... W15]; Wnd ∈ [W0 ... W14]
Operation:	If Byte Mode: {24{Ws[7]}}, Ws[7:0] → Wnd[31:0] If Word Mode: {16{Ws[15]}}, Ws[15:0] → Wnd[31:0]
Status Affected:	C,N,Z
Encoding:	`S111`	`110B`	`dddd`	`ssss`	`pppU`	`UUww`	`wwUU`	`UU00`
Description:	Sign-extend an 8-bit or 16-bit signed value in Ws to a 32-bit signed value, then write the result back to Wnd. C is set to the complement of N. The ‘S’ bit selects instruction size. The ‘B’ bit selects byte or word operation. The ‘s’ bits select the source register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘w’ bits define the offset Wb. Note: This operation always writes a long word. Unlike all other Word mode instructions, word data does not always zero extend.
I-Words:	1 or 0.5
Cycles:	1


SE.b W0, W3

Before execution		After execution
W0	0x00000089	W0	0x00000089
W3	0x00000000	W3	0xFFFFFF89

SR[7:0]	8'b00000000	SR[7:0]	8'b00000000


SE W0, W3

Before execution		After execution
W0	0x12347879	W0	0x12347879
W3	0x00000000	W3	0x00007879

SR[7:0]	8'b00000000	SR[7:0]	8'b00001000	(N = 1)


SETM		Set f
Syntax:	{label:}	SETM.b	f
		SETM{.w}
		SETM.l





Operands:	f ∈ [0 ... 1MB]
Operation:	0xFFFFFFFF → file register for long operation 0xFFFF → file register for word operation 0xFF → file register for byte operation
Status Affected:	None
Encoding:	`1010`	`111L`	`ffff`	`ffff`	`ffff`	`ffff`	`ffff`	`B101`
Description:	Set the file register. The ‘L’ and ‘B’ bits select operation data width. The ‘f’ bits select the address of the file register. Note: Accessible file address space is 1MB.
I-Words:	1
Cycles:	1


SFTAC		Arithmetic Shift Accumulator
Syntax:	{label:}	SFTAC{.w} A,		Ws
		SFTAC.l	B,	[Ws]
				[Ws++]
				[Ws--]
				[++Ws]
				[--Ws]
				[Ws+Wb]

Operands:	Ws ∈ [W0 ... W15]; Wb ∈ [W0 ... W15]
Operation:	Shift_(Ws)(ACC)
Status Affected:	OA, SA or OB, SB
Encoding:	`1100`	`11AL`	`wwww`	`ssss`	`pppU`	`UUUU`	`UUUU`	`0011`
Description:	Arithmetic shift of accumulator. The shift value is sourced from the word or long word signed contents of Ws[5:0]. If Ws is positive or zero, the shift will be a right shift of between 1 and 31 bits maximum (or no shift if Ws is 0). If Ws is negative, the shift will be a left shift of between 1 and 32 bits maximum. If Ws is out of range (i.e., when Ws[15:5] for word, or Ws[31:5] for long word are not equal to all 1’s or all 0’s), a math error trap will be requested during execution. The instruction will continue to execute but the result will not be written to the destination accumulator, and the SR will not be modified. The ‘L’ bit selects word or long word Ws (shift count). The ‘A’ bit selects the accumulator for the result. The ‘s’ bits select the Ws register. The ‘p’ bits select the source addressing mode. The ‘w’ bits define the offset Wb.
I-Words:	1
Cycles:	1


SFTAC		Arithmetic Shift Accumulator
Syntax:	{label:}	SFTAC	A,	Slit6
			B,






Operands:	Slit6 ∈ [-32 ... 31]
Operation:	Shift_k(ACC)
Status Affected:	OA, SA or OB, SB
Encoding:	`1100`	`11AU`	`UUUU`	`UUUU`	`UUUU`	`UUkk`	`kkkk`	`0111`
Description:	Arithmetic shift of accumulator. The Slit6 is used as the shift amount. If Slit6 is positive or zero, the shift will be a right shift of between 0 and 31 bits maximum. If Slit6 is negative, the shift will be a left shift of between 1 and 32 bits maximum. The ‘A’ bit selects the accumulator for the result. The ‘k’ bits determine the number of bits to be shifted.
I-Words:	1
Cycles:	1


SL	Shift Left by 1
Syntax:	{label:}	SL.b	Ws,	Wd
		SL.bz	[Ws],	[Wd]
		SL{.w}	[Ws++],	[Wd++]
		SL.l	[Ws--],	[Wd--]
			[++Ws],	[++Wd]
			[--Ws],	[--Wd]


Operands:	Ws ∈ [W0 ... W15]; Wd ∈ [W0 ... W15]
Operation:	For long word operation: (Ws[31]) → C, (Ws[30:0]) → Wd[31:1], 0 → Wd[0] For word operation: (Ws[15]) → C, (Ws[14:0]) → Wd[15:1], 0 → Wd[0] For byte operation: (Ws[7]) → C, (Ws[6:0]) → Wd[7:1], 0 → Wd[0]
Status Affected:	C,N,Z
Encoding:	`S010`	`110L`	`dddd`	`ssss`	`pppq`	`qqUU`	`UUUU`	`B000`
Description:	Shift left the contents of the source register Ws by 1 bit, placing the result in the destination register Wd. Destination register direct Extended Byte or Word mode will zero-extend the result to 32-bits, then write to Wd. The ‘S’ bit selects instruction size. The ‘L’ and ‘B’ bits select operation data width.  The ‘s’ bits select the source register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode.
I-Words:	1 or 0.5
Cycles:	1


SL		Shift Left f
Syntax:	{label:}	SL.b	f	{,Wnd}	{,WREG}
		SL.bz
		SL{.w}
		SL.l




Operands:	f ∈ [0 ... 64KB]; Wnd ∈ [W0 ... W14]
Operation:	For byte operation: (f<7>) → (C), (f[6:0]) → Dest[7:1], 0 → Dest[0] For word operation: (f[15]) → (C), (f[14:0]) → Dest[15:1], 0 → Dest[0] For long word operation: (f[31]) → (C), (f[30:0]) → Dest[31:1], 0 → Dest[0]
Status Affected:	C, N, Z
Encoding:	`1010`	`010L`	`dddd`	`ffff`	`ffff`	`ffff`	`ffff`	`BD01`
Description:	Shift the contents of the file register f one bit to the left with a ‘0’ fill. The carry flag is set if the MSB of f is ‘1’. Place the result in the destination designated by D. If the optional Wnd is specified, D = 0 and store result in Wnd; otherwise, D = 1 and store result in the file register. The ‘L’ and ‘B’ bits select operation data width. The ‘D’ bit selects the destination. The ‘f’ bits select the address of the file register. The ‘d’ bits select the Working register.
I-Words:	1
Cycles:	1


Example 1:	SL.B 0x909				; Shift left (0x909) (Byte mode)
		Before Instruction				After Instruction
Data 0908			9439	Data 0908		0839
	SR		0000		SR	0001	(C = 1)


Example 2:	SL 0x1650, WREG
		Before Instruction				After Instruction
WREG (W0)			0900	WREG (W0)		80CA
Data 1650			4065	Data 1650		4065
	SR		0000		SR	0008	(N = 1)


SL		Shift Left by Short Literal
Syntax:	{label:}	SL{.w}	Ws,	lit5,	Wd
		SL.l	[Ws],		[Wd]
			[Ws++],		[Wd++]
			[Ws--],		[Wd--]
			[++Ws],		[--Wd]
			[--Ws],		[++Wd]

Operands:	Ws ∈ [W0 ... W14]; lit5 ∈ [0...31]; Wd ∈ [W0 ... W14]
Operation:	lit5[4:0]→ Shift_Val 1’b0 → Left shift input For long word operation: 32’b0,Ws[31:0] → Shift_In[63:0] Shift left Shift_In[63:0] by Shift_Val → Shift_Out[63:0] Shift_Out[31:0] → Wnd For word operation: 48’b0, Ws[15:0], → Shift_In[63:0] Shift left Shift_In[63:0] by Shift_Val → Shift_Out[63:0] Shift_Out[15:0] → Wnd[15:0]
Status Affected:	N,Z
Encoding:	`S010`	`010k`	`kkkk`	`dddd`	`pppq`	`qqss`	`ssUU`	`LU00`
Description:	Shift left the contents of the source register Ws by lit5 bits (up to 31 positions), placing the result in the destination Wd. This instruction will generate the correct result for any shift value in lit5 (a word operation shift value > 15, Wnd[15:0]=0x0000). When used in conjunction with the SLMK instruction for multi-precision multi-bit shift operations, this instruction will not generate a correct result for any shift value greater than 32. Register Direct Word mode will zero-extend the result to 32-bits, then write to Wd. The ‘S’ bit selects instruction size. The ‘L’ bit selects word or long word operation. The ‘s’ bits select the source register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode. The ‘k’ bits provide the literal operand. Note: This instruction only operates in Word or Long Word mode.
I-Words:	1 or 0.5
Cycles:	1


Example 1:	SL W2, #4, W2
		Before Instruction				After Instruction
W2			78A9	W2		8A90
	SR		0000		SR	0008	(N = 1)


Example 2:	SL W3, #12, W8
		Before Instruction				After Instruction
W3			0912	W3		0912
W8			1002	W8		2000
	SR		0000		SR	0000


SL	Shift Left by Wb
Syntax:	{label:}	SL.b	Ws,	Wb,	Wd
		SL.bz	[Ws],		[Wd]
		SL{.w}	[Ws++],		[Wd++]
		SL.l	[Ws--],		[Wd--]
			[++Ws],		[++Wd]
			[--Ws],		[--Wd]


Operands:	Ws ∈ [W0 ... W15]; Wb ∈ [W0 ...W15]; Wd ∈ [W0 ... W15]
Operation:	Wb[15:0]→ Shift_Val For long word operation: 32’b0, Ws[31:0] → Shift_In[63:0] Shift left Shift_ln[63:0] by Shift_Val → Shift_Out[63:0] Shift_Out[31:0] → Wd For word operation: 48’b0, Ws[15:0] → Shift_In[63:0] Shift left Shift_ln[63:0] by Shift_Val → Shift_Out[63:0] Shift_Out[15:0] → Wd For byte operation: 56’b0, Ws[7:0] → Shift_In[63:0] Shift left Shift_ln[63:0] by Shift_Val → Shift_Out[63:0] Shift_Out[7:0] → Wd
Status Affected:	N,Z
Encoding:	`1010`	`110L`	`wwww`	`dddd`	`pppq`	`qqss`	`ssUU`	`B100`
Description:	Shift left the contents of the source register Ws by Wb bits, placing the result in the destination register Wd. When used in isolation, this instruction will generate the correct result for any shift value in Wb[15:0]: For a byte operation shift value > 7, Wd[7:0]=0x00 For a word operation shift value > 15, Wd[15:0]=0x0000 For a long word operation shift value > 31, Wd=0x00000000 When used in conjunction with the SLMW instruction for multi-precision multi-bit shift operations, this instruction will not generate a correct result for any shift value greater than 32. Any data held in Wb[31:16] will have no effect. Destination register direct Extended Byte or Word mode will zero-extend the result to 32-bits, then write to Wd. The ‘L’ and ‘B’ bits select operation data width.  The ‘s’ bits select the source register. The ‘w’ bits select the base (shift count) register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode.
I-Words:	1
Cycles:	1


SLAC		Store Lower Accumulator
Syntax:	{label:}	SLAC{.l}	A,	{ Slit6 , }	Wd
			B,		[Wd]
					[Wd++]
					[Wd--]
					[--Wd]
					[++Wd]
					[Wd+Wb]


Operands:	Slit6 ∈ [-32 ... +31]; Wd ∈ [W0 ... W15] (see note 2); Wb ∈ [W0 ... W15]
Operation:	Shift_Slit6(ACC) (ACC[31:0]) → Wd[31:0]
Status Affected:	None
Encoding:	`1100`	`01A1`	`wwww`	`dddd`	`UUUq`	`qqkk`	`kkkk`	`0111`
Description:	Read then optionally shift accumulator value, then store post-shift ACC[31:0] to the destination Effective Address. Any shift will apply only to data read from the accumulator so will not modify the accumulator contents. The shift value is sourced from a signed literal value. The ‘A’ bit specifies the source accumulator. The ‘d’ bits specify the destination register Wd. The ‘q’ bits select the destination addressing mode. The ‘w’ bits specify the offset register Wb. The ‘k’ bits encode the optional operand Slit6 which determines the amount of the accumulator shift. If operand Slit6 is absent, set literal to all 0’s. Note: Positive values of operand Slit6 represent arithmetic shift right. Negative values of operand Slit6 represent shift left. Register direct destination W15 not permitted.
I-Words:	1
Cycles:	1


SLAC A, #4, w8

Before execution		After execution
ACCA	0xFF_9022_2EE1_5633_9078	ACCA	0xFF_9022_2EE1_5633_9078
w8	0x00000000	w8	0x05633907


SLM		Shift Left Multi-Precision by Short Literal
Syntax:	{label:}	SLM{.l}	Ws,	lit5,	Wnd
			[Ws],
			[Ws++],
			[Ws--],
			[++Ws],
			[--Ws],


Operands:	Ws ∈ [W0 ... W15]; lit5 ∈ [0...31]; Wnd ∈ [W0 ... W13]
Operation:	lit5[4:0]→ Shift_Val 0 → Left shift input 32’b0,Ws[31:0] → Shift_In[63:0] Shift left Shift_In[63:0] by Shift_Val → Shift_Out[63:0] Shift_Out[31:0] → Wnd Shift_Out[63:32] \| Wnd+1 → Wnd+1
Status Affected:	Z
Encoding:	`1110`	`000k`	`kkkk`	`dddd`	`pppU`	`UUss`	`ssUU`	`1011`
Description:	Shift left the contents of the source register Ws by lit5 bits (up to 31 positions), placing the result in the destination register Wnd. The register containing the next most significant data word will already contain an intermediate shift result. Bitwise OR this value with the data shifted out of Ws in order to create the final shift result, then update the corresponding destination register. This instruction is intended to be used in conjunction with the SLK instruction to support multi-precision multi-bit shift operations. The Z bit is “sticky” (can only be cleared). The ‘s’ bits select the source register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘k’ bits provide the literal operand. Note: This instruction operates in Long Word mode only.
I-Words:	1
Cycles:	2


SLAC	A, #4, w8

Before execution		After execution
ACCA	0xFF_9022_2EE1_5633_9078	ACCA	0xFF_9022_2EE1_5633_9078
w8	0x00000000	w8	0x56339078


SLM		Shift Left Multi-Precision by Wb
Syntax:	{label:}	SLM{.l}	Ws,	Wb,	Wnd
			[Ws],
			[Ws++],
			[Ws--],
			[++Ws],
			[--Ws],


Operands:	Ws ∈ [W0 ... W15]; Wb ∈ [W0 ...W15]; Wnd ∈ [W0 ... W13]
Operation:	Wb[15:0]→ Shift_Val 0 → Left shift input 32’b0,Ws[31:0] → Shift_In[63:0] Shift left Shift_In[63:0] by Shift_Val → Shift_Out[63:0] Shift_Out[31:0] → Wnd Shift_Out[63:32] \| Wnd+1 → Wnd+1
Status Affected:	Z
Encoding:	`1110`	`001U`	`ssss`	`dddd`	`pppU`	`UUww`	`wwUU`	`1011`
Description:	Shift left the contents of the source register Ws by Wb bits, placing the result in the destination register Wnd. The register containing the next most significant data word will already contain an intermediate shift result. Bitwise OR this value with the data shifted out of Ws in order to create the final shift result, then update the corresponding destination register. The left shift may be by any amount between 0 and 32 bits. Should the shift value held in Wb[15:0] exceed 2’d32, the shift value will saturate to 2’d32 for consistency. Any data held in Wb[31:16] will have no effect. This instruction is intended to be used in conjunction with the SLW instruction to support multi-precision multi-bit shift operations. The Z bit is “sticky” (can only be cleared). The ‘w’ bits select the base (shift count) register. The ‘s’ bits select the source register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. Note: This instruction operates in Long Word mode only.
I-Words:	1
Cycles:	2


SQR		Square to Accumulator
Syntax: {label}	SQR{.w}	Wx,	A	{,AWB}
	SQR.l	[Wx],	B
		[Wx]+=kx,
		[Wx]-=kx,
		[Wx+=kx],
		[Wx-=kx],
		[Wx+W12],



Operands:	Wx ∈ {W0 ... W15}; Word mode: kx ∈ {-8, -6, -4, -2, 2, 4, 6, 8}; Long Word mode: kx ∈ {-16, -12, -8, -4, 4, 8, 12, 16}; AWB ∈ {W0, W1, W2, W3, W13, [W13++], [W15++]⁵}
Operation:	(Wx)² → ACC(A or B); (ACC(B or A)) rounded → AWB When Indirect Pre/Post Modification Addressing: (Wx)+kx→Wx or (Wx)-kx→Wx;
Status Affected:	OA,SA or OB,SB
Encoding:	`1101`	`01AL`	`wwww`	`ssss`	`IIIi`	`i110`	`UUaa`	`a011`
Description:	Instruction to compute (A)² functions. Signed or unsigned (defined by CORCON.US) square of data read from Wx or fetched from the X address space. Note that, because only one operand is required, DS is not split into the X and Y address space for concurrent read access, so X-space in this instruction represents all of available DS (which will include Y-space). The result is sign-extended or zero-extended to 72-bits then written to the specified accumulator. Fractional results are also scaled prior to the accumulator update to align the operand and accumulator (msw) fractional points. When Indirect Pre/Post Modified Addressing is selected, the address modifier value is kx, and represents the number of data bytes by which to modify the Effective Address. The optional AWB specifies the direct or indirect store of the (32-bit) rounded fractional contents of the accumulator not targeted by the SQR operation. Rounding mode is defined by CORCON.RND. Write data width is determined by selected instruction data size (see note 4). AWB is not intended for use when the DSP engine is operating in Integer mode. Data read may be 16-bit or 32-bit values. All indirect address modification is scaled accordingly. The ‘L’ bit selects word or long word operation. The ‘A’ bit selects the accumulator for the result. The ‘I’ bits select the Operation.Addressing mode. The ‘i’ bits select the kx modification value. The ‘s’ bits select Wx, data register or X-space source address register. The ‘w’ bits are to be a copy of the ‘s’ bits. The ‘a’ bits select the accumulator write-back destination and addressing mode. Note: Operates in Fractional or Integer Data mode as defined by CORCON.IF. Operands are always regarded as signed or unsigned based on the state of CORCON.US. Use of the same W-reg for both indirect source and AWB indirect destination is not permitted if the source is a pre- or post-modified Effective Address. Stack must remain long word aligned. Consequently, [W15++] AWB is only permitted for use with long word MAC-class instructions.
I-Words:	1
Cycles:	1


SQR.l	[w9]+=4, A

Before execution		After execution
ACCA	0x00_7022_2EE1_5633_9078	ACCA	0x00_1000_0000_0000_0000
w9	0x5000	w9	0x5000
Data @5000	0x20000000	Data @5000	0x20000000


SQRAC		Square and Accumulate
Syntax: {label}	SQRAC{.w} Wx,		A	{,AWB}
	SQRAC.l [Wx],		B
		[Wx]+=kx,
		[Wx]-=kx,
		[Wx+=kx],
		[Wx-=kx],
		[Wx+W12],



Operands:	Wx ∈ {W0 ... W15}; Word mode: kx ∈ {-8, -6, -4, -2, 2, 4, 6, 8}; Long Word mode: kx ∈ {-16, -12, -8, -4, 4, 8, 12, 16}; AWB ∈ {W0, W1, W2, W3, W13, [W13++], [W15++]⁵}
Operation:	ACC(A or B) + (Wx)² → ACC(A or B); (ACC(B or A)) rounded → AWB When Indirect Pre/Post Modification Addressing: (Wx)+kx→Wx or (Wx)-kx→Wx;
Status Affected:	OA,SA or OB,SB
Encoding:	`1101`	`00AL`	`wwww`	`ssss`	`IIIi`	`i110`	`UUaa`	`a011`
Description:	Instruction to compute Accumulator + (A)² functions. Signed or unsigned (defined by CORCON.US) square of data read from Wx or fetched from the X address space. Note that, because only one operand is required, DS is not split into X and Y address space for concurrent read access, so X-space in this instruction represents all of the available DS (which will include Y-space). The result is sign-extended or zero-extended to 72-bits then added to the specified accumulator. Fractional or integer operation (defined by CORCON.IF) will determine if the result is scaled or not prior to the accumulator update. Fractional operation will scale the result to align the operand and accumulator (msw) fractional points (see note 3). Integer operation will align the LSb of the result with the LSb of the accumulator. When indirect pre/post modified addressing is selected, the address modifier value is kx and represents the number of data bytes by which to modify the Effective Address. The optional AWB specifies the direct or indirect (see note 4) store of the (32-bit) rounded fractional contents of the accumulator not targeted by the SQRAC operation. Rounding mode is defined by CORCON.RND. Write data width is determined by selected instruction data size. AWB is not intended for use when the DSP engine is operating in Integer mode. Data read may be 16-bit or 32-bit values. All indirect address modification is scaled accordingly. The ‘L’ bit selects word or long word operation. The ‘A’ bit selects the accumulator for the result. The ‘I’ bits select the Operation.Addressing mode. The ‘i’ bits select the kx modification value. The ‘s’ bits select Wx, data register or X-space source address register. The ‘w’ bits are to be a copy of the ‘s’ bits. The ‘a’ bits select the accumulator write-back destination and addressing mode. Note: Operates in Fractional or Integer Data mode as defined by CORCON.IF. Operands are always regarded as signed or unsigned based on the state of CORCON.US. The LS portion of ACCx is unaffected when operating in Fractional mode with word sized data. Lower significance data that may be present from prior (32-bit data) operations is therefore preserved. Users not requiring this should clear ACCx during initialization. Use of the same W-reg for both indirect source and AWB indirect destination is not permitted if the source is a pre- or post-modified Effective Address. Stack must remain long word aligned. Consequently, [W15++] AWB is only permitted for use with long word MAC-class instructions.
I-Words:	1
Cycles:	1


SQRAC.l [w9]+=4, A

Before execution		After execution
ACCA	0x00_4000_0000_0000_0000	ACCA	0x00_5000_0000_0000_0000
w9	0x5000	w9	0x5000
Data @5000	0x20000000	Data @5000	0x20000000


SQRN		Negated Square to Accumulator
Syntax: {label}	SQRN{.w} Wx,		A	{,AWB}
	SQRN.l	[Wx],	B
		[Wx]+=kx,
		[Wx]-=kx,
		[Wx+=kx],
		[Wx-=kx],
		[Wx+W12],



Operands:	Wx ∈ {W0 ... W15}; Word mode: kx ∈ {-8, -6, -4, -2, 2, 4, 6, 8}; Long Word mode: kx ∈ {-16, -12, -8, -4, 4, 8, 12, 16}; AWB ∈ {W0, W1, W2, W3, W13, [W13++], [W15++]⁵}
Operation:	-(Wx)² → ACC(A or B); (ACC(B or A)) rounded → AWB When Indirect Pre/Post Modification Addressing: (Wx)+kx→Wx or (Wx)-kx→Wx;
Status Affected:	OA,SA or OB,SB
Encoding:	`1101`	`01AL`	`wwww`	`ssss`	`IIIi`	`i110`	`UUaa`	`a111`
Description:	Instruction to compute -(A)² functions. Signed or unsigned (defined by CORCON.US) square of data read from Wx or fetched from the X address space. Note that, because only one operand is required, DS is not split into X and Y address space for concurrent read access, so X-space in this instruction represents all of the available DS (which will include Y-space). The result is sign-extended or zero-extended to 72-bits, negated and then written to the specified accumulator. Fractional results are also scaled prior to the accumulator update to align the operand and accumulator (msw) fractional points. For word sized operand operations, when Indirect Pre/Post Modified Addressing is selected, the address modifier value is kx and represents the number of data bytes by which to modify the Effective Address. The optional AWB specifies the direct or indirect (see note 3) store of the (32-bit) rounded fractional contents of the accumulator not targeted by the SQRN operation. Rounding mode is defined by CORCON.RND. Write data width is determined by selected instruction data size (see note 4). AWB is not intended for use when the DSP engine is operating in Integer mode. Data read may be 16-bit or 32-bit values. All indirect address modification is scaled accordingly. The ‘L’ bit selects word or long word operation. The ‘A’ bit selects the accumulator for the result. The ‘I’ bits select the Operation.Addressing mode. The ‘i’ bits select the kx modification value. The ‘s’ bits select Wx, data register or X-space source address register. The ‘w’ bits are to be a copy of the ‘s’ bits. The ‘a’ bits select the accumulator write-back destination and addressing mode. Note: Operates in Fractional or Integer Data mode as defined by CORCON.IF. Use of the same W-reg for both indirect source and AWB indirect destination is not permitted if the source is a pre- or post-modified Effective Address. Use of the same W-reg for both indirect source and AWB indirect destination is not permitted if the source is a pre- or post-modified Effective Address. Stack must remain long word aligned. Consequently, [W15++] AWB is only permitted for use with long word MAC-class instructions.
I-Words:	1
Cycles:	1


SQRN.l	[w9]+=4, A

Before execution		After execution
ACCA	0x00_4000_0000_0000_0000	ACCA	0xFF_F000_0000_0000_0000
w9	0x5000	w9	0x5000
Data @5000	0x20000000	Data @5000	0x20000000


SQRSC		Square and Subtract from Accumulator
Syntax: {label}	SQRSC{.w} Wx,		A	{,AWB}
	SQRSC.l [Wx],		B
		[Wx]+=kx,
		[Wx]-=kx,
		[Wx+=kx],
		[Wx-=kx],
		[Wx+W12],



Operands:	Wx ∈ {W0 ... W15}; Word mode: kx ∈ {-8, -6, -4, -2, 2, 4, 6, 8}; Long Word mode: kx ∈ {-16, -12, -8, -4, 4, 8, 12, 16}; AWB ∈ {W0, W1, W2, W3, W13, [W13++], [W15++]⁵}
Operation:	ACC(A or B) - (Wx)² → ACC(A or B); (ACC(B or A)) rounded → AWB When Indirect Pre/Post Modification Addressing: (Wx)+kx→Wx or (Wx)-kx→Wx;
Status Affected:	OA,SA or OB,SB
Encoding:	`1101`	`00AL`	`wwww`	`ssss`	`IIIi`	`i110`	`UUaa`	`a111`
Description:	Instruction to compute Accumulator - (A)² functions. Signed or unsigned (defined by CORCON.US) square of data read from Wx or fetched from the X address space. Note that, because only one operand is required, DS is not split into X and Y address space for concurrent read access, so X-space in this instruction represents all of the available DS (which will include Y-space). The result is sign-extended or zero-extended to 72-bits then subtracted from the specified accumulator. Fractional or integer operation (defined by CORCON.IF) will determine if the result is scaled or not prior to the accumulator update. Fractional operation will scale the result to align the operand and accumulator (msw) fractional points (see note 4). Integer operation will align the LSb of the result with the LSb of the accumulator. When Indirect Pre/Post Modified Addressing is selected, the address modifier value is kx and represents the number of data bytes by which to modify the Effective Address. The optional AWB specifies the direct or indirect (see note 4) store of the (32-bit) rounded fractional contents of the accumulator not targeted by the SQRSC operation. Rounding mode is defined by CORCON.RND. Write data width is determined by selected instruction data size. AWB is not intended for use when the DSP engine is operating in Integer mode. Data read may be 16-bit or 32-bit values. All indirect address modification is scaled accordingly. The ‘L’ bit selects word or long word operation. The ‘A’ bit selects the accumulator for the result. The ‘I’ bits select the Operation.Addressing mode. The ‘i’ bits select the kx modification value. The ‘s’ bits select Wx, data register or X-space source address register. The ‘w’ bits are to be a copy of the ‘s’ bits. The ‘a’ bits select the accumulator write-back destination and addressing mode. Note: Operates in Fractional or Integer Data mode as defined by CORCON.IF. Operands are always regarded as signed or unsigned based on the state of CORCON.US. Use of the same W-reg for both indirect source and AWB indirect destination is not permitted if the source is a pre- or post-modified Effective Address. The LS portion of ACCx is unaffected when operating in Fractional mode with word sized data. Lower significance data that may be present from prior (32-bit data) operations is therefore preserved. Users not requiring this should clear ACCx during initialization. Stack must remain long word aligned. Consequently, [W15++] AWB is only permitted for use with long word MAC-class instructions.
I-Words:	1
Cycles:	1


SQRSC.l	[w9]+=4, A

Before execution		After execution
ACCA	0x00_4000_0000_0000_0000	ACCA	0x00_3000_0000_0000_0000
w9	0x5000	w9	0x5000
Data @5000	0x20000000	Data @5000	0x20000000


SACR		Store Rounded Accumulator, Literal Shift
Syntax:	{label:}	SACR{.w} A,		{ Slit6, }	Wd
		SACR.l	B,		[Wd]
					[Wd++]
					[Wd--]
					[--Wd]
					[++Wd]
					[Wd+Wb]

Operands:	Slit6 ∈ [-32 ... +31]; Wd ∈ [W0 ... W15]; Wb ∈ [W0 ... W15];
Operation:	For long word operation: Long Word mode: Post-shift(Round{ACC[63:32]}) → Wd[31:0] For word operation: Word mode: Post-shift(Round{ACC[63:48]}) → Wd[15:0] ¹
Status Affected:	None
Encoding:	`1100`	`01AL`	`wwww`	`dddd`	`UUUq`	`qqkk`	`kkkk`	`1011`
Description:	Perform an optional, signed 6-bit shift of the specified accumulator, then store the rounded contents of Acc[63:32] (in case of long-word operation) or Acc[63:48]( in case of word operation) to Wd. The shift range is -32:31, where a negative operand indicates an arithmetic left shift and a positive operand indicates an arithmetic right shift. The Rounding mode (Conventional or Convergent) is set by the RND bit (CORCON<1>). Either Register Direct or Indirect Addressing may be used for Wd. The ‘L’ bit selects word or long word operation. The ‘A’ bit specifies the source accumulator. The ‘d’ bits specify the destination register Wd. The ‘q’ bits select the destination addressing mode. The ‘w’ bits specify the offset register Wb. The ‘k’ bits encode the optional operand Slit6 which determines the amount of the accumulator shift. If operand Slit6 is absent, set literal to all 0’s. Note: When the destination is register direct (W-reg), the result is either zero extended (CORCON.US = 1) or sign extended (CORCON.US = 0) to 32 bits. Register direct destination W15 not permitted.
I-Words:	1
Cycles:	1


SACR	B, #-1, w8

Before execution		After execution
ACCB	0x00_1022_2EE1_5633_9078	ACCB	0x00_1022_2EE1_5633_9078
w8	0x00000000	w8	0x00007022


SACR.l	A, #1, w8

Before execution		After execution
ACCA	0x00_7022_2EE1_5633_9078	ACCA	0x00_7022_2EE1_5633_9078
w8	0x00000000	w8	0x70222EE1


SACR		Store Rounded Accumulator after Shift
Syntax:	{label:}	SACR{.w} A,		Ws,	Wd
		SACR.l	B,		[Wd]
					[Wd++]
					[Wd--]
					[--Wd]
					[++Wd]
					[Wd+Wb]

Operands:	Ws ∈ [W0 ... W15]; Wd ∈ [W0 ... W15] (see note 2); Wb ∈ [W0 ... W15];
Operation:	For long word operation: Long Word mode: Post-shift(Round{ACC[63:32]}) → Wd[31:0] For word operation: Word mode: Post-shift(Round{ACC[63:48]}) → Wd[15:0] ¹
Status Affected:	None
Encoding:	`1100`	`10AL`	`wwww`	`dddd`	`UUUq`	`qqss`	`ssUU`	`0111`
Description:	Perform an optional, signed 6-bit shift of the specified accumulator, then store the rounded contents of Acc[63:32] (in case of long-word operation) or Acc[63:48] ( in case of word operation) to Wd. The shift range is sourced from the singed contents of Ws[5:0], values in the range of -32:31, where a negative value indicates an arithmetic left shift and a positive value indicates an arithmetic right shift. The Rounding mode (Conventional or Convergent) is set by the RND bit (CORCON<1>). Either Register Direct or Indirect Addressing may be used for Wd. If Ws is out of range (that is., Ws[31:5] not equal to all 1’s or all 0’s), a math error trap will be requested during execution. The instruction will continue to execute based on the value held in Ws[5:0]. After the shift, a word operation (SACR.w) assumes that the value is a Q1.15 signed fraction. Accordingly, a round into shift result bit 48 is executed and shift result [63:48] is then written to the Effective Address. After the shift, a long word operation (SACR.l) assumes that the value is a Q1.31 signed fraction. Accordingly, a round into shift result bit 32 is executed and shift result [63:32] is then written to the Effective Address. The ‘L’ bit selects word or long word operation. The ‘A’ bit specifies the source accumulator. The ‘d’ bits specify the destination register Wd. The ‘s’ bits specify the shift value source register Ws. The ‘q’ bits select the destination addressing mode. The ‘w’ bits specify the offset register Wb. See for modifier addressing information. Note: When the destination is register direct (W-reg), the result is either zero extended (CORCON.US = 1) or sign extended (CORCON.US = 0) to 32-bits. Register direct destination W15 not permitted.
I-Words:	1
Cycles:	1


SACR.l	A, W9, w8

Before execution		After execution
ACCA	0x00_7022_2EE1_5633_9078	ACCA	0x00_7022_2EE1_5633_9078
w8	0x00000000	w8	0x70222EE1
w9	0x1	w9	0x1


SUAC		Store Upper Accumulator
Syntax:	{label:}	SUAC{.l}	A,	{ Slit6 , }	Wd
			B,		[Wd]
					[Wd++]
					[Wd--]
					[--Wd]
					[++Wd]
					[Wd+Wb]


Operands:	Slit6 ∈ [-32 ... +31]; Wd ∈ [W0 ... W15] (see note 2); Wb ∈ [W0 ... W15]
Operation:	Shift_Slit6(ACC) (24{ACC[71]}, ACC[71:64]) → Wd[31:0]
Status Affected:	None
Encoding:	`1100`	`01A1`	`wwww`	`dddd`	`UUUq`	`qqkk`	`kkkk`	`1111`
Description:	Read then optionally shift accumulator value, then store the post-shifted upper byte (ACC[71:64]) to the destination Effective Address. Any shift will apply only to data read from the accumulator so will therefore not modify the accumulator contents. The shift value is sourced from a signed literal value. When the destination is register direct (W-reg), the byte result is either zero extended (CORCON.US = 1) or sign extended (CORCON.US = 0) to 32 bits prior to the write. The ‘A’ bit specifies the source accumulator. The ‘d’ bits specify the destination register Wd. The ‘q’ bits select the destination addressing mode. The ‘w’ bits specify the offset register Wb. The ‘k’ bits encode the optional operand Slit6 which determines the amount of the accumulator shift. If operand Slit6 is absent, set literal to all 0’s. Note: Positive values of operand Slit6 represent arithmetic shift right. Negative values of operand Slit6 represent shift left. Register direct destination W15 not permitted.
I-Words:	1
Cycles:	1


SACR.l	A, W9, w8

Before execution		After execution
ACCA	0xC1_1022_2EE1_5633_9078	ACCA	0xC1_1022_2EE1_5633_9078
w8	0x12345678	w8	0xFFFFFFFC


SUB		Subtract Ws from Wb
Syntax:	{label:}	SUB.b	Wb,	Ws,	Wd
		SUB.bz		[Ws],	[Wd]
		SUB{.w}		[Ws++],	[Wd++]
		SUB.l		[Ws--],	[Wd--]
				[++Ws],	[++Wd]
				[--Ws],	[--Wd]


Operands:	Wb ∈ [W0 ... W15]; Ws ∈ [W0 ... W15]; Wd ∈ [W0 ... W15]
Operation:	(Wb) - (Ws) → Wd
Status Affected:	C, N, OV, Z
Encoding:	`S110`	`010L`	`dddd`	`ssss`	`pppq`	`qqww`	`wwUU`	`BU00`
Description:	Subtract the contents of the source register Ws from the contents of the base register Wb and place the result in the destination register Wd. The ‘S’ bit selects instruction size. The ‘L’ and ‘B’ bits select operation data width. The ‘s’ bits select the source register. The ‘w’ bits select the base register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode.
I-Words:	1 or 0.5
Cycles:	1


Example 1:	SUB.B W0, W1, W0
		Before Instruction				After Instruction
W0			1732	W0		17EE
W1			7844	W1		7844
	SR		0000		SR	0108	(DC, N = 1)


Example 2:	SUB W7, [W8++], [W9++]
		Before Instruction				After Instruction
W7			2450	W7		2450
W8			1808	W8		180A
W9			2020	W9		2022
Data 1808			92E4	Data 1808		92E4
Data 2020			A557	Data 2020		916C
	SR		0000		SR	010C	(DC, N, OV = 1)


SUB		Subtract Accumulators
Syntax:	{label:}	SUB	A
			B






Operands:	none
Operation:	if (SUB A) then ACCA - ACCB → ACCA if (SUB B) then ACCB - ACCA → ACCB
Status Affected:	OA, SA or OB, SB
Encoding:	`0111`	`001A`	`UUUU`	`1001`
Description:	Subtract accumulators and write results to selected accumulator. The ‘A’ bit specifies the destination accumulator.
I-Words:	0.5
Cycles:	1


SUB	A

Before execution		After execution
ACCA	0x76_120F_098A_1212_4593	ACCA	0x52_CC7B_E055_7FDD_B56A
ACCB	0x23_4593_2934_9234_9029	ACCB	0x23_4593_2934_9234_9029
CORCON	0x00000000	CORCON	0x0000000

SR[15:8]	8'b00000000	SR[15:8]	8'b11000000	(OA/OB = 1)


SUB	B

Before execution		After execution
ACCA	0xFF_9022_2EE1_5633_9078	ACCA	0xFF_9022_2EE1_5633_9078
ACCB	0x00_2456_8F4C_0922_1245	ACCB	0x00_7FFF_FFFF_FFFF_FFFF
CORCON	0x00000040	CORCON	0x00000040	(SATB)

SR[15:8]	8'b00000000	SR[15:8]	8'b00010100	(SB/SAB = 1)


Example 1:	w8, #1, B	;ACCB = ACCB - (w8>>1):32'b0
	Before Execution		After Execution
w8	0x20446326	w8	0x20446326
ACCB	0x00_2044_6326_4112_9403	ACCB	0x00_1022_3193_4112_9403


SUB		Signed Subtract from Accumulator
Syntax:	{label:}	SUB{.w} Ws,		{ Slit6, }	A
		SUB.l	[Ws],		B
			[Ws++]
			[Ws--]
			[--Ws],
			[++Ws],
			[Ws+Wb],

Operands:	Ws ∈ [W0 ... W15]; Wb ∈ [W0 ... W15]; Slit6 ∈ [-32 ... +31]
Operation:	(ACC) - Shift_Slit6(Sign-extend(Ws)) → ACC
Status Affected:	OA, SA or OB, SB
Encoding:	`1100`	`00AL`	`wwww`	`ssss`	`pppU`	`UUkk`	`kkkk`	`1111`
Description:	The operand contained at the Effective Address is assumed to be Q1.15 or Q1.31 fractional data for word and long data operations, respectively. The operand is read, then automatically sign-extended and zero-backfilled to create a value the same size as the accumulator. The value is then optionally (arithmetically) shifted before being subtracted from the target accumulator. The ‘L’ bit selects word or long word operation. The ‘A’ bit specifies the destination accumulator. The ‘s’ bits specify the source register Ws. The ‘p’ bits select the source addressing mode. The ‘w’ bits specify the offset register Wb. The ‘k’ bits encode the optional operand Slit6 which determines the amount of the accumulator preshift; if the operand Slit6 is absent, the literal bit field is set to all 0’s. Note: Positive values of operand Slit6 represent arithmetic shift right. Negative values of operand Slit6 represent shift left. This instruction operates in Long or Word mode only.
I-Words:	1
Cycles:	1


SUB	w8, #1, B

Before execution		After execution
w8	0x20446326	w8	0x20446326
ACCB	0x00_2044_6326_4112_9403	ACCB	0x00_1022_3193_4112_9403


SUB		;ACCA = ACCA - ACCB ; CORCON = 0x0000 (no saturation)

Before execution		After execution
ACCA	0x76_120F_098A_1212_4593	ACCA	0x52_CC7B_E055_7FDD_B56A
ACCB	0x23_4593_2934_9234_9029	ACCB	0x23_4593_2934_9234_9029
CORCON	0x00000000	CORCON	0x0000000

SR[15:8]	8'b00000000	SR[15:8]	8'b11000000	(OA/OB = 1)


SUB		;ACCB = ACCB - ACCA ; CORCON = 0x0000 (no saturation

Before execution		After execution
ACCA	0xFF_9022_2EE1_5633_9078	ACCA	0xFF_9022_2EE1_5633_9078
ACCB	0x00_2456_8F4C_0922_1245	ACCB	0x00_7FFF_FFFF_FFFF_FFFF
CORCON	0x00000040	CORCON	0x00000040	(SATB)

SR[15:8]	8'b00000000	SR[15:8]	8'b00010100	(SB/SAB = 1)


SUBB		Subtract Ws from Wb with Borrow
Syntax:	{label:}	SUBB.b	Wb,	Ws,	Wd
		SUBB.bz		[Ws],	[Wd]
		SUBB{.w}		[Ws++],	[Wd++]
		SUBB.l		[Ws--],	[Wd--]
				[++Ws],	[++Wd]
				[--Ws],	[--Wd]


Operands:	Wb ∈ [W0 ... W15]; Ws ∈ [W0 ... W15]; Wd ∈ [W0 ... W15]
Operation:	(Wb) - (Ws) - (C) → Wd
Status Affected:	C, N, OV, Z
Encoding:	`S110`	`011L`	`dddd`	`ssss`	`pppq`	`qqww`	`wwUU`	`BU00`
Description:	Subtract the contents of the source register Ws and the Carry flag from the contents of the base register Wb and place the result in the destination register Wd. The Z bit is “sticky” (can only be cleared). The ‘S’ bit selects instruction size . The ‘L’ and ‘B’ bits select operation data width. The ‘s’ bits select the source register. The ‘w’ bits select the base register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode.
I-Words:	1 or 0.5
Cycles:	1


Example 1:	SUBB.B W0, W1, W0						; Sub. W1 and C from W0 (Byte mode) ; Store result to W0
		Before Instruction			After Instruction
W0			1732	W0		17ED
W1			7844	W1		7844
	SR		0000		SR	0108	(DC, N = 1)


Example 2:	`SUBB W7,[W8++],[W9++]`
		Before Instruction				After Instruction
W7			2450	W7		2450
W8			1808	W8		180A
W9			2022	W9		2024
Data 1808			92E4	Data 1808		92E4
Data 2022			A557	Data 2022		916B
	SR		0000		SR	010C	(DC, N, OV = 1)


SUBB		Subtract Short Literal from Ws with Borrow
Syntax:	{label:}	SUBB.b	Ws,	lit7,	Wd
		SUBB.bz	[Ws],		[Wd]
		SUBB{.w}	[Ws++],		[Wd++]
		SUBB.l	[Ws--],		[Wd--]
			[++Ws],		[++Wd]
			[--Ws],		[--Wd]


Operands:	Ws ∈ [W0 ... W15]; lit7 ∈ [0 ... 127]; Wd ∈ [W0 ... W15]
Operation:	(Ws) - lit7 - (C) → Wd Note: The literal is zero-extended to the selected data size of the operation
Status Affected:	C, N, OV, Z
Encoding:	`1110`	`011L`	`dddd`	`ssss`	`pppq`	`qqkk`	`kkkk`	`Bk10`
Description:	Subtract the zero-extended unsigned literal operand and the Carry bit from the contents of the source register Ws, and place the result in the destination register Wd. The Z bit is “sticky” (can only be cleared). The ‘L’ and ‘B’ bits select operation data width. The ‘k’ bits provide the literal operand (MSb in op[2]). The ‘s’ bits select the source register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode.
I-Words:	1
Cycles:	1


SUBB		Subtract Literal from Wn with Borrow
Syntax:	{label:}	SUBB.b	lit16,	Wn
		SUBB.bz
		SUBB{.w}
		SUBB.l




Operands:	lit16 ∈ [0 ... 65535]; Wn ∈ [W0 ... W15]
Operation:	(Wn) - lit16 - (C) → Wn Note: The literal is zero-extended to the selected data size of the operation
Status Affected:	C, N, OV, Z
Encoding:	`1100`	`011L`	`ssss`	`kkkk`	`kkkk`	`kkkk`	`kkkk`	`B010`
Description:	Subtract the zero-extended literal operand and the Carry bit from the contents of the Working register Wn, and place the result in the Working register Wn. In Byte mode, only the LSb of Wn is written. In Word mode, the word result is zero-extended to 32-bits and written to Wn. The Z bit is “sticky” (can only be cleared). The ‘L’ and ‘B’ bits select operation data width. The ‘s’ bits select the Working register. The ‘k’ bits specify the literal operand.
I-Words:	1
Cycles:	1


SUBBR		Subtract f and Carry bit from Wn
Syntax:	{label:}	SUBBR.b f		,Wn	{,WREG}
		SUBBR.bz
		SUBBR{.w}
		SUBBR.l




Operands:	f ∈ [0 ... 64KB]; Wn ∈ [W0 ... W15]
Operation:	(Wn) - (f) - (C) → destination designated by D
Status Affected:	C, N, OV, Z
Encoding:	`1110`	`011L`	`ssss`	`ffff`	`ffff`	`ffff`	`ffff`	`BD01`
Description:	Subtract the contents of the file register and the Carry bit from the contents of the Working register and place the result in the destination designated by D. If the optional Wn is specified, D=0 and store result in Wn; otherwise, D=1 and store result in the file register. The Z bit is “sticky” (can only be cleared). The ‘L’ and ‘B’ bits select operation data width. The ‘D’ bit selects the destination. The ‘f’ bits select the address of the file register. The ‘s’ bits select the Working register.
I-Words:	1
Cycles:	1


SUBBR		Subtract Wb from Ws with Borrow
Syntax:	{label:}	SUBBR.b	Wb,	Ws,	Wd
		SUBBR.bz		[Ws],	[Wd]
		SUBBR{.w}		[Ws++],	[Wd++]
		SUBBR.l		[Ws--],	[Wd--]
				[++Ws],	[++Wd]
				[--Ws],	[--Wd]


Operands:	Wb ∈ [W0 ... W15]; Ws ∈ [W0 ... W15]; Wd ∈ [W0 ... W15]
Operation:	(Ws) - (Wb) - (C) → Wd
Status Affected:	C, N, OV, Z
Encoding:	`S110`	`111L`	`dddd`	`ssss`	`pppq`	`qqww`	`wwUU`	`BU00`
Description:	Subtract the contents of the base register Wb and the Carry flag from the contents of the source register Ws, and place the result in the destination register Wd. The Z bit is “sticky” (can only be cleared). The ‘S’ bit selects instruction size. The ‘L’ and ‘B’ bits select operation data width. The ‘s’ bits select the source register. The ‘w’ bits select the base register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode.
I-Words:	1 or 0.5
Cycles:	1


Example 1:	SUBBR.B W0, W1, W0				; Sub. W0 and C from W1 (Byte mode) ; Store result to W0
		Before Instruction				After Instruction
W0			1732	W0		1711
W1			7844	W1		7844
	SR		0000		SR	0001	(C = 1)


Example 2:	SUBBR W7,[W8++],[W9++]				; Sub. W7 and C from [W8] (Word mode) ; Store result to [W9] ; Post-increment W8 ; Post-increment W9
		Before Instruction				After Instruction
W7			2450	W7		2450
W8			1808	W8		180A
W9			2022	W9		2024
Data 1808			92E4	Data 1808		92E4
Data 2022			A557	Data 2022		6E93
	SR		0000		SR	0005	(OV, C = 1)


SUBBR		Subtract Ws from Short Literal with Borrow
Syntax:	{label:}	SUBBR.b	Ws,	lit7	Wd
		SUBBR.bz [Ws],			[Wd]
		SUBBR{.w} [Ws++],			[Wd++]
		SUBBR.l	[Ws--],		[Wd--]
			[++Ws],		[++Wd]
			[--Ws],		[--Wd]


Operands:	Ws ∈ [W0 ... W15]; lit7 ∈ [0 ... 127; Wd ∈ [W0 ... W15] Note: The literal is zero-extended to the selected data size of the operation
Operation:	lit7 - (Ws) - (C) → Wd
Status Affected:	C, N, OV, Z
Encoding:	`1110`	`111L`	`dddd`	`ssss`	`pppq`	`qqkk`	`kkkk`	`Bk10`
Description:	Subtract the contents of the source register Ws and the Carry flag from the zero-extended unsigned literal, and place the result in the destination register Wd. The Z bit is “sticky” (can only be cleared). The ‘L’ and ‘B’ bits select operation data width. The ‘k’ bits provide the literal operand (MSb in op[2]). The ‘s’ bits select the source register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode.
I-Words:	1
Cycles:	1


SUBB		Subtract Wn and Carry bit from f
Syntax:	{label:}	SUBB.b	f	,Wn	{,WREG}
		SUBB.bz
		SUBB{.w}
		SUBB.l




Operands:	f ∈ [0 ... 64KB]; Wn ∈ [W0 ... W15]
Operation:	(f) - (Wn) - (C) → destination designated by D
Status Affected:	C, N, OV, Z
Encoding:	`1110`	`111L`	`ssss`	`ffff`	`ffff`	`ffff`	`ffff`	`BD01`
Description:	Subtract the contents of the Working register and the Carry bit from the contents of the file register, and place the result in the destination designated by D. If the optional Wn is specified, D=0 and store result in Wn; otherwise, D=1 and store result in the file register. The Z bit is “sticky” (can only be cleared). The ‘L’ and ‘B’ bits select operation data width. The ‘D’ bit selects the destination. The ‘f’ bits select the address of the file register. The ‘s’ bits select the Working register.
I-Words:	1
Cycles:	1


SUB		Subtract f from Wn
Syntax:	{label:}	SUBR.b	f	,Wn	{,WREG}
		SUBR.bz
		SUBR{.w}
		SUBR.l




Operands:	f ∈ [0 ... 64KB]; Wn ∈ [W0 ... W15]
Operation:	(Wn) - (f) → destination designated by D
Status Affected:	C, N, OV, Z
Encoding:	`1110`	`010L`	`ssss`	`ffff`	`ffff`	`ffff`	`ffff`	`BD01`
Description:	Subtract the contents of the file register from the contents of the Working register, and place the result in the destination designated by D. If the optional Wn is specified, D=0 and store result in Wn; otherwise, D=1 and store result in the file register. The ‘L’ and ‘B’ bits select operation data width. The ‘D’ bit selects the destination. The ‘f’ bits select the address of the file register. The ‘s’ bits select the Working register.
I-Words:	1
Cycles:	1


SUB			Subtract Short Literal from Wn
Syntax:	{label:}	SUB.l	lit5,	Wn




Operands:	lit5 ∈ [0 ... 31]; Wn ∈ [W0 ... W15]
Operation:	(Wn) - lit5 → Wn
Status Affected:	C, N, OV, Z
Encoding:	`0111`	`011k`	`kkkk`	`ssss`
Description:	Subtract the zero-extended literal operand from the contents of the Working register and place the result in the Working register Wn. If literal >31 and/or word or byte operation is required, assemble as SUBLW instruction. The ‘s’ bits select the Working register. The ‘k’ bits specify the literal operand.
I-Words:	0.5
Cycles:	1


SUB		Subtract Short Literal from Ws
Syntax:	{label:}	SUB.b	Ws,	lit7,	Wd
		SUB.bz	[Ws],		[Wd]
		SUB{.w}	[Ws++],		[Wd++]
		SUB.l	[Ws--],		[Wd--]
			[++Ws],		[++Wd]
			[--Ws],		[--Wd]


Operands:	Ws ∈ [W0 ... W15]; lit7 ∈ [0 ... 127]; Wd ∈ [W0 ... W15]
Operation:	(Ws) - lit7 → Wd Note: The literal is zero-extended to the selected data size of the operation
Status Affected:	C, N, OV, Z
Encoding:	`1110`	`010L`	`dddd`	`ssss`	`pppq`	`qqkk`	`kkkk`	`Bk10`
Description:	Subtract the zero-extended unsigned literal operand from the contents of the source register Ws, and place the result in the destination register Wd. The ‘L’ and ‘B’ bits select operation data width. The ‘k’ bits provide the literal operand (MSb in op[2]). The ‘s’ bits select the source register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode.
I-Words:	1
Cycles:	1


SUB			Subtract Literal from Wn
Syntax:	{label:}	SUB.b	lit16,	Wn
		SUB.bz
		SUB{.w}
		SUB.l




Operands:	lit16 ∈ [0 ... 65535]; Wn ∈ [W0 ... W15]
Operation:	(Wn) - lit16 → Wn
Status Affected:	C, N, OV, Z
Encoding:	`1100`	`010L`	`ssss`	`kkkk`	`kkkk`	`kkkk`	`kkkk`	`B010`
Description:	Subtract the zero-extended literal operand from the contents of the Working register, and place the result in the Working register Wn. If literal <=31 and long operation is required, assemble as SUBLN instruction. The ‘L’ and ‘B’ bits select operation data width. The ‘s’ bits select the Working register. The ‘k’ bits specify the literal operand.
I-Words:	1
Cycles:	1


Example 1:	SUB.B #0x23, W0
		Before Instruction				After Instruction
W0			7804	W0		78E1
	SR		0000		SR	0008	(N = 1)


Example 2:	SUB #0x108, W4
		Before Instruction				After Instruction
W4			6234	W4		612C
	SR		0000		SR	0001	(C = 1)


SUBR		Subtract Wb from Ws
Syntax:	{label:}	SUBR.b	Wb,	Ws,	Wd
		SUBR.bz		[Ws],	[Wd]
		SUBR{.w}		[Ws++],	[Wd++]
		SUBR.l		[Ws--],	[Wd--]
				[++Ws],	[++Wd]
				[--Ws],	[--Wd]


Operands:	Wb ∈ [W0 ... W15]; Ws ∈ [W0 ... W15]; Wd ∈ [W0 ... W15]
Operation:	(Ws) - (Wb) → Wd
Status Affected:	C, N, OV, Z
Encoding:	`S110`	`110L`	`dddd`	`ssss`	`pppq`	`qqww`	`wwUU`	`BU00`
Description:	Subtract the contents of the base register Wb from the contents of the source register Ws, and place the result in the destination register Wd. The ‘S’ bit selects instruction size. The ‘L’ and ‘B’ bits select operation data width. The ‘s’ bits select the source register. The ‘w’ bits select the base register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode.
I-Words:	1 or 0.5
Cycles:	1


Example 1:	SUBR.B W0, W1, W0						; Sub. W0 from W1 (Byte mode) ; Store result to W0
		Before Instruction			After Instruction
W0			1732	W0		1712
W1			7844	W1		7844
	SR		0000		SR	0001	(C = 1)


Example 2:	SUBR W7, [W8++], [W9++]
		Before Instruction				After Instruction
W7			2450	W7		2450
W8			1808	W8		180A
W9			2022	W9		2024
Data 1808			92E4	Data 1808		92E4
Data 2022			A557	Data 2022		6E94
	SR		0000		SR	0005	(OV, C = 1)


SUBR		Subtract Ws from Short Literal
Syntax:	{label:}	SUBR.b	Ws,	lit7,	Wd
		SUBR.bz	[Ws],		[Wd]
		SUBR{.w} [Ws++],			[Wd++]
		SUBR.l	[Ws--],		[Wd--]
			[++Ws],		[++Wd]
			[--Ws],		[--Wd]


Operands:	Ws ∈ [W0 ... W15]; Wd ∈ [W0 ... W15]; lit7 ∈ [1 ... 63] (see note when lit7 = 0)
Operation:	lit7 - (Ws) → Wd Note: The literal is zero-extended to the selected data size of the operation
Status Affected:	C, N, OV, Z
Encoding:	`S111`	`101L`	`dddd`	`ssss`	`pppq`	`qqkk`	`kkkk`	`Bk00`
Description:	Subtract the contents of the source register Ws from the zero-extended unsigned literal, and place the result in the destination register Wd. The ‘S’ bit selects instruction size. The ‘L’ and ‘B’ bits select operation data width. The ‘k’ bits provide the literal operand (MSb in op[2]). The ‘s’ bits select the source register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode.
I-Words:	1 or 0.5
Cycles:	1


SUB		Subtract Wn from f
Syntax:	{label:}	SUB.b	f	Wn	{,WREG}
		SUB.bz
		SUB{.w}
		SUB.l




Operands:	f ∈ [0 ... 64KB]; Wn ∈ [W0 ... W15]
Operation:	(f) - (Wn) → destination designated by D
Status Affected:	C, N, OV, Z
Encoding:	`1110`	`110L`	`ssss`	`ffff`	`ffff`	`ffff`	`ffff`	`BD01`
Description:	Subtract the contents of the Working register from the contents of the file register, and place the result in the destination designated by D. If the optional Wn is specified, D=0 and store the result in Wn; otherwise, D=1 and store the result in the file register. The ‘L’ and ‘B’ bits select operation data width. The ‘D’ bit selects the destination. The ‘f’ bits select the address of the file register. The ‘s’ bits select the Working register.
I-Words:	1
Cycles:	1


SWAP		Word, Byte or Nibble Swap Wn
Syntax:	{label:}	SWAP.b	Wn
		SWAP.bz
		SWAP{.w}
		SWAP.l




Operands:	Wn ∈ [W0 ... W15]
Operation:	Byte mode: Wn[7:4] ↔ Wn[3:0] Extended Byte mode: Wn[7:4] ↔ Wn[3:0]; 24’h000000 → Wn[31:8] Word mode: Wn[15:8] ↔ Wn[7:0] Long Word mode: Wn[31:24] ↔ Wn[7:0]; Wn[23:16] ↔ Wn[15:8]
Status Affected:	None
Encoding:	`1111`	`011L`	`UUUU`	`ssss`	`UUUU`	`UUUU`	`UUUU`	`B111`
Description:	If in Long Word mode, swap bytes in both the msw and lsw of Wn register. If in Word mode, swap bytes in the lsw of Wn register. Wn[31:16] is cleared. If in Extended Byte mode, swap nibbles in the LSb of Wn register. Wn[31:8] is cleared. If in Byte mode, swap nibbles in the LSb of Wn register. Wn[31:8] is unaffected. The ‘L’ and ‘B’ bits select operation data width. The ‘s’ bits select the Working register. Long word byte swap is intended for data endian conversion.
I-Words:	1
Cycles:	1


TSTF		Test f and (optionally) Move to Wd
Syntax:	{label:}	TST.b	f	{,Wnd}
		TST.bz
		TST{.w}
		TST.l




Operands:	f ∈ [0 ... 64KB]; Wnd ∈ [W0 ... W14];
Operation:	(f) → destination designated by D
Status Affected:	Z, N
Encoding:	`1101`	`001L`	`dddd`	`ffff`	`ffff`	`ffff`	`ffff`	`BD01`
Description:	Read and test the contents of the file register. If the optional Wnd is specified (D=0), then store the data read in Wnd. Otherwise, D=1 and the only effect is to modify the status flags (i.e, test file register), and no write occurs. The ‘L’ and ‘B’ bits select operation data width. The ‘D’ bit selects if a data write occurs. The ‘f’ bits select the address of the file register.
I-Words:	1
Cycles:	1


ULNK		De-allocate Stack Frame
Syntax:	{label:}	ULNK







Operands:	None
Operation:	W14 → W15 (W15) - 4 → W15 (TOS) → W14
Status Affected:	None
Encoding:	`0111`	`001U`	`UUUU`	`0011`
Description:	This instruction de-allocates a stack frame and adjusts the Stack Pointer and Frame Pointer. Note: This instruction operates with long word aligned operands only.
I-Words:	0.5
Cycles:	1


Example 1:	ULNK
		Before Instruction			After Instruction
W14			0x5004	W14		0x5000
W15			0x502C	W15		0x5000
Data @0x5000			0x5000	Data @0x5000		0x5000

	SR[7:0]		8'b00000000		SR[7:0]	8'b00000001


XOR		Exclusive or Wb and Ws
Syntax:	{label:}	XOR.b	Wb,	Ws,	Wd
		XOR.bz		[Ws],	[Wd]
		XOR{.w}		[Ws++],	[Wd++]
		XOR.l		[Ws--],	[Wd--]
				[++Ws],	[++Wd]
				[--Ws],	[--Wd]
				SR	SR

Operands:	Wb ∈ [W0 ... W15]; Ws ∈ [W0 ... W15]; Wd ∈ [W0 ... W15]
Operation:	(Wb).XOR.(Ws) → Wd
Status Affected:	N, Z
Encoding:	`S111`	`000L`	`dddd`	`ssss`	`pppq`	`qqww`	`wwUU`	`BU00`
Description:	Compute exclusive OR of the contents of the source register Ws and the contents of the base register Wb, and place the result in the destination register Wd. The ‘S’ bit selects instruction size. The ‘L’ and ‘B’ bits select operation data width. The ‘s’ bits select the source register. The ‘w’ bits select the base register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode. Note: When the SR is selected, SR data write will take priority over any SR update resulting from the XOR operation. .bz data size/mode is disallowed when writing to the SR.
I-Words:	1 or 0.5
Cycles:	1


Example 1:	XOR.B W1, [W5++], [W9++]							; XOR W1 and [W5] (Byte mode) ; Store result to [W9] ; Post-increment W5 and W9
		Before Instruction					After Instruction
W1			AAAA		W1			AAAA
W5			2000		W5			2001
W9			2600		W9			2601
Data 2000			115A	Data 2000				115A
Data 2600			0000	Data 2600				00F0
	SR		0000			SR		0008	(N = 1)


Example 2:	XOR W1, W5, W9				; XOR W1 and W5 (Word mode) ; Store the result to W9
		Before Instruction				After Instruction
W1			FEDC	W1			FEDC
W5			1234	W5			1234
W9			A34D	W9			ECE8
	SR		0000		SR		0008	(N = 1)


XOR		Exclusive Or Ws and Short Literal
Syntax:	{label:}	XOR.b	Ws,	lit7,	Wd
		XOR.bz	[Ws],		[Wd]
		XOR{.w}	[Ws++],		[Wd++]
		XOR.l	[Ws--],		[Wd--]
			[++Ws],		[++Wd]
			[--Ws],		[--Wd]
			SR		SR

Operands:	Ws ∈ [W0 ... W15]; lit7 ∈ [0 ... 127]; Wd ∈ [W0 ... W15]
Operation:	(Ws).XOR.lit7 → Wd Note: The literal is zero-extended to the selected data size of the operation
Status Affected:	N, Z
Encoding:	`1111`	`000L`	`dddd`	`ssss`	`pppq`	`qqkk`	`kkkk`	`Bk10`
Description:	Compute the exclusive OR of the contents of the source register Ws and the zero-extended literal operand, and place the result in the destination register Wd. The ‘L’ and ‘B’ bits select operation data width. The ‘k’ bits provide the literal operand (MSb in op[2]). The ‘s’ bits select the source register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘q’ bits select the destination addressing mode. Note: When the SR is selected, SR data write will take priority over any SR update resulting from the XOR operation. .bz data size/mode is disallowed when writing to the SR.
I-Words:	1
Cycles:	1


XOR		Exclusive Or Literal and Wn
Syntax:	{label:}	XOR.b	lit16,	Wn
		XOR.bz		SR
		XOR{.w}
		XOR.l




Operands:	lit16∈ [0 ... 65535]; Wn ∈ [W0 ... W15]; Status Register (SR)
Operation:	(Wn) .XOR. lit16 → Wn or (SR) .XOR. lit16 → SR
Status Affected:	N, Z
Encoding:	`1101`	`000L`	`ssss`	`kkkk`	`kkkk`	`kkkk`	`kkkk`	`BT10`
Description:	Compute the exclusive OR of the zero-extended literal operand and the contents of the Working register Wn or SR, and place the result in the Working register Wn or SR. The ‘L’ and ‘B’ bits select operation data width. The ‘s’ bits select the Working register. The ‘k’ bits specify the literal operand. The ‘T’ bit selects between Ws (T = 0) and SR (T = 1) target registers. Note: When the SR is selected, SR data write will take priority over any SR update resulting from the XOR operation. .bz data size/mode is disallowed when writing to the SR.
I-Words:	1
Cycles:	1


Example 1:	XOR.B #0x23, W0
		Before Instruction				After Instruction
W0			7804	W0			7827
	SR		0000		SR		0000


Example 2:	XOR #0x108, W4
		Before Instruction				After Instruction
W4			6134	W4			603C
	SR		0000		SR		0000


XOR		Exclusive Or f and Wn
Syntax:	{label:}	XOR.b	f	,Wn	{,WREG}
		XOR.bz
		XOR{.w}
		XOR.l




Operands:	f ∈ [0 ... 64KB]; Wn ∈ [W0 ... W15]
Operation:	(f).XOR.(Wn) → destination designated by D
Status Affected:	N, Z
Encoding:	`1111`	`000L`	`ssss`	`ffff`	`ffff`	`ffff`	`ffff`	`BD01`
Description:	Compute the XOR of the contents of the Working register and the contents of the file register, and place the result in the destination designated by D: If the optional Wn is specified, D=0 and store the result in Wn; otherwise, D=1 and store the result in the file register. The ‘L’ and ‘B’ bits select operation data width. The ‘D’ bit selects the destination. The ‘f’ bits select the address of the file register. The ‘s’ bits select the Working register.
I-Words:	1
Cycles:	1


ZE		Zero Extend Ws
Syntax:	{label:}	ZE.bz	Ws,	Wnd
		ZE.w	[Ws],
			[Ws++],
			[Ws--],
			[++Ws],
			[--Ws],
			[Ws+Wb],

Operands:	Ws ∈ [W0 ... W15]; Wb ∈ [W0 ... W15]; Wnd ∈ [W0 ... W14]
Operation:	If Byte mode: Ws[7:0] → Wd[7:0]; 0 → Wnd[31:8]; If Word mode: Ws[15:0] → Wd[15:0]; 0 → Wnd[31:16];
Status Affected:	C, N, Z
Encoding:	`S111`	`111B`	`dddd`	`ssss`	`pppU`	`UUww`	`wwUU`	`UU00`
Description:	Zero-extend an 8-bit or 16-bit signed value in Ws to a 32-bit value, then write the result back to Wnd. N is always cleared. C is always set. The ‘S’ bit selects instruction size. The ‘B’ bit selects byte or word operation. The ‘s’ bits select the source register. The ‘d’ bits select the destination register. The ‘p’ bits select the source addressing mode. The ‘w’ bits define the offset Wb. Note: This operation always writes a long word.
I-Words:	1 or 0.5
Cycles:	1


Example 1:			W0, W3		;Zero extend a byte in W0, store it in W3
	Before Instruction			After Instruction
W0		0x12347879	W0		0x12347879
W3		0x00000000	W3		0x00000079
SR[7:0]		8'b00000000	SR		8'b00000001	(C = 1)


Example 2:			W0, W3		;Zero extend a word in W0, store it in W3
	Before Instruction			After Instruction
W0		0x12347879	W0		0x12347879
W3		0x00000000	W3		0x00007879

SR[7:0]		8'b00000000	SR[7:0]		8'b00000001	(C = 1)