4.4 Instruction Descriptions (A to BZ)

The ‘A’ bits specify the destination accumulator.

Note: The literal is zero-extended to the selected data size of the operation

The Z bit is “sticky” (can only be cleared).

The ‘L’ and ‘B’ bits select operation data width.

The ‘s’ bits select the Working register.

The ‘k’ bits specify the signed literal operand.

The Z bit is “sticky” (can only be cleared).

The ‘L’ and ‘B’ bits select operation data width.

The ‘D’ bit selects the destination.

The ‘f’ bits select the address of the file register.

The ‘s’ bits select the Working register.

Note: The literal is zero-extended to the selected data size of the operation

The ‘s’ bits select the Working register.

The ‘k’ bits specify the signed literal operand.

Note: The literal is zero-extended to the selected data size of the operation

The ‘L’ and ‘B’ bits select operation data width.

The ‘k’ bits provide the literal operand.

The ‘s’ bits select the source register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

The ‘q’ bits select the destination addressing mode.

Note: The literal is zero-extended to the selected data size of the operation

The ‘L’ and ‘B’ bits select operation data width.

The ‘s’ bits select the Working register.

The ‘k’ bits specify the signed literal operand.

The ‘L’ and ‘B’ bits select operation data width.

The ‘D’ bit selects the destination.

The ‘f’ bits select the address of the file register.

The ‘s’ bits select the Working register.

The ‘S’ bit selects instruction size.

The ‘L’ and ‘B’ bits select operation data width.

The ‘s’ bits select the source register.

The ‘w’ bits select the base register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

The ‘q’ bits select the destination addressing mode.

See and for modifier addressing information.

The ‘L’ and ‘B’ bits select operation data width.

The ‘k’ bits provide the unsigned literal operand.

The ‘s’ bits select the source register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

The ‘q’ bits select the destination addressing mode.

The ‘L’ and ‘B’ bits select operation data width.

The ‘k’ bits provide the unsigned literal operand.

The ‘s’ bits select the source register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

The ‘q’ bits select the destination addressing mode.

The ‘L’ and ‘B’ bits select operation data width.

The ‘s’ bits select the Working register.

The ‘k’ bits specify the unsigned literal operand.

The ‘T’ bit selects between Ws (T = 0) and SR (T = 1) target registers.

The ‘L’ and ‘B’ bits select operation data width.

The ‘D’ bit selects the destination.

The ‘f’ bits select the address of the file register.

The ‘s’ bits select the Working register.

(Ws[31]) → Wd[31], (Ws[31:1]) → Wd[30:0], (Ws[0]) → C

For word operation:

(Ws[15]) → Wd[15], (Ws[15:1]) → Wd[14:0], (Ws[0]) → C

For byte operation:

(Ws[7]) → Wd[7], (Ws[7:1]) → Wd[6:0], (Ws[0]) → C

Destination register direct Extended Byte or Word mode will zero-extend the result to 32-bits, then write to Wd.

The ‘S’ bit selects instruction size.

The ‘L’ and ‘B’ bits select operation data width.
 The ‘s’ bits select the source register.

The ‘w’ bits select the base register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

The ‘q’ bits select the destination addressing mode.

(f[31]) → Dest[31], (f[31]) → Dest[30],

(f[30:1]) → Dest[29:0], (f[0]) → C

For word operation:

(f[15]) → Dest[15], (f[15]) → Dest[14]

(f[14:1]) → Dest[13:0], (f[0]) → C

For byte operation:

(f[7]) → Dest[7:1], (f[7]) → Dest[6],

(f[6:1]) → Dest[5:0], (f[0]) → C

The ‘L’ and ‘B’ bits select operation data width.

The ‘D’ bit selects the destination.

The ‘f’ bits select the address of the file register.

The ‘d’ bits select the Working register.

For long word operation:

Ws[31] → Right shift input (arithmetic shift)

Ws[31:0], 32’b0 → Shift_In[63:0]

Arithmetic shift right Shift_In[63:0] by Shift_Val → Shift_Out[63:0]

Shift_Out[63:32] → Wd

For word operation:

Ws[15] → Right shift input (arithmetic shift)

{16{Ws[15]}}, Ws[15:0],32’b0 → Shift_In[63:0]

Arithmetic shift right Shift_In[63:0] by Shift_Val → Shift_Out[63:0]

Shift_Out[47:32] → Wd[15:0]

Arithmetic shift right the contents of the source register Ws by lit5 bits (up to 31 positions), placing the result in the destination Wd.

This instruction will generate the correct result for a word operation with any shift value in lit5. If lit5 > 15 and Ws[15] = 0, then Wd[15:0]=0x0000.
If lit5 > 15 and Ws[15] = 1, then Wd[15:0]=0xFFFF.

Register Direct Word mode will zero-extend the result to 32-bits, then write to Wd.

The ‘S’ bit selects instruction size.

The ‘L’ bit selects word or long word operation.

The ‘s’ bits select the source register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

The ‘q’ bits select the destination addressing mode.

The ‘k’ bits provide the literal operand.

I-Words: 1 or 0.5 Cycles: 1

Ws[31] → Right shift input (arithmetic shift)

Ws[31:0], 32’b0 → Shift_In[63:0]

Arithmetic shift right Shift_In[63:0] by Shift_Val → Shift_Out[63:0]

Shift_Out[63:32] → Wnd

Shift_Out[31:0] | Wnd-1 → Wnd-1

Arithmetic shift right the contents of the source register Ws by lit5 bits (up to 31 positions), placing the result in the destination register Wnd. The register containing the next least significant data word will already contain an intermediate shift result. Bitwise OR this value with the data shifted out of Ws in order to create the final shift result, then update the corresponding destination register.

The Z bit is “sticky” (can only be cleared).

The ‘s’ bits select the source register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

The ‘k’ bits provide the literal operand.

1. Note: This instruction only operates in Long Word mode.

Ws[31] → Right shift input (arithmetic shift)

Ws[31:0], 32’b0 → Shift_In[63:0]

Arithmetic shift right Shift_In[63:0] by Shift_Val → Shift_Out[63:0]

Shift_Out[63:32] → Wnd

Shift_Out[31:0] | Wnd-1 → Wnd-1

The arithmetic right shift may be by any amount between 0 and 32 bits. Should the shift value held in Wb[15:0] exceed 2’d32, the shift value will saturate to 2’d32 for consistency. Any data held in Wb[31:16] will have no effect.

The Z bit is “sticky” (can only be cleared).

The ‘w’ bits select the base (shift count) register.

The ‘s’ bits select the source register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

If (condition) then {

If slit20 = 1 then skip next (16-bit) instruction

Else If (slit20 = 2 && next_op[31] = 1) then skip next (32-bit) instruction

Else (PC+4) + 2*slit20 → PC

}

Else no branch

If the 2’s complement byte offset value ‘2*slit20’ (the PC offset) equals two, the conditional branch will execute as a conditional skip of one 16-bit instruction. This instruction will be speculatively executed as not skipped until such time that the branch decision can be determined.

If the 2’s complement byte offset value ‘2*slit20’ (the PC offset) equals four, and the instruction after the branch is a 32-bit opcode (see note), the conditional branch will execute as a conditional skip of that 32-bit instruction. This instruction will be speculatively executed as not skipped until such time that the branch decision can be determined.

If requirements for a conditional skip are not met, the 2’s complement byte offset value ‘2*slit20’ is added to the PC to create a new PS word address. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+4) + 2*slit20.

Branch prediction is based on the direction of the branch. If the branch is backwards (negative), it will be predicted as taken. If the branch is forwards (positive), it will be predicted as not taken. The two instructions that follow the branch will then be speculatively executed in the predicted path until such time that the actual branch decision can be assessed. A correctly predicted branch will continue instruction execution in the same path unabated. An incorrectly predicted branch will abort the speculatively executed instructions and start execution from the correct path.

The ‘n’ bits are a signed literal that specifies the number of PS words offset from (PC+4).


Byte: bit5 ∈ [0 ... 7];

Word: bit5 ∈ [0 ... 15];

Long word: bit5 ∈ [0 ... 31]

The ‘S’ bit selects instruction size.

The ‘L’ and ‘B’ bits select operation data width.

The ‘b’ bits define value or bit5 of the bit position to be cleared (bit5[4:0] for the 16-bit opcode).

The ‘s’ bits select the source/destination register.

The ‘p’ bits select the source addressing mode.

The ‘w’ bits select value bit3 of the bit position to be cleared.

The ‘f’ bits select the address of the file register.

Long: bit5 ∈ [0 .. 31]; wid6 ∈ [0 .. 32]
Ws ∈ [W0 ... W15]; Wb ∈ [W0 ... W14]

The bit location within Ws of the LSb of the bit field to be extracted is defined by operand bit5. The width of the bit field is defined by operand wid6 and may be between zero and up to 16-bits (word operation) or 32-bits (long word operation).

Word mode will zero-extend the result to 32-bits prior to the write to Wb.

The ‘L’ bit selects word or long word operation.

The ‘w’ bits select the bit field destination register.

The ‘s’ bits select the data source register.

The ‘p’ bits select the source addressing mode.

The ‘ccccc’ bits define the bit field LSb position within the target word.

The ‘mmmmm’ bits define the bit field MSb position within the target word.

The bit location within the file register of the LSb of the bit field to be extracted is defined by operand bit5. The width of the bit field is defined by operand wid6 and may be between 0 and up to 16-bits (word operation) or 32-bits (long word operation).

Word mode will zero-extended the result to 32-bits and then write to Wb.

The ‘L’ bit selects word or long word operation.

The ‘w’ bits select the bit field destination register.

The ‘f’ bits select the address of the source file register.

The ‘ccccc’ bits define the bit field LSb position within the target word.

The ‘mmmmm’ bits define the bit field MSb position within the target word.

Long: bit5 ∈ [0 .. 31]; wid6 ∈ [0 .. 32]
Wb ∈ [W0 ... W14]; Ws ∈ [W0 ... W15]

The inserted bit field will overwrite the bits already in Ws or SR (i.e., the instruction does not shift any existing bits to accommodate the new bit field).

The bit location within Ws of the LSb of the bit field to be inserted is defined by operand bit5. The width of the bit field is defined by operand wid6 and may be between zero and up to 16-bits (word operation) or 32-bits (long word operation).

Word mode will zero-extend a Ws register direct result write to 32-bits.

The ‘L’ bit selects word or long word operation.

The ‘w’ bits select the bit field source register.

The ‘s’ bits select the data source/destination register.

The ‘p’ bits select the source addressing mode.

The ‘ccccc’ bits define the bit field LSb position within the target word.

The ‘mmmmm’ bits define the bit field MSb position within the target word.

Long: bit5 ∈ [0 .. 31]; wid6 ∈ [0 .. 32]
Wb ∈ [W0 ... W14]; f ∈ [0 ... 1MB]

The inserted bit field will overwrite the bits already in the file register (i.e., the instruction does not shift any existing bits to accommodate the new bit field).

The bit location within the file register of the LSb of the bit field to be inserted is defined by operand bit5. The width of the bit field is defined by operand wid6 and may be between zero and up to 16-bits (word operation) or 32-bits (long word operation).

The ‘w’ bits select the bit field source register.

The ‘f’ bits select the source/destination file register.

The ‘ccccc’ bits define the bit field LSb position within the target word.

The ‘mmmmm’ bits define the bit field MSb position within the target word.

The inserted bit field will overwrite the bits already in Ws (i.e., the instruction does not shift any existing bits to accommodate the new bit field).

The bit location within Ws of the LSb of the bit field to be inserted is defined by operand bit5. The width of the bit field is defined by operand wid6 and may be between zero and up to 16-bits (word operation) or 32-bits (long word operation).

Word mode will zero-extend a Ws register direct result write to 32-bits.

The ‘L’ bit selects word or long word operation.

The ‘k’ bits contain the bit field source value.

The ‘s’ bits select the source/destination register.

The ‘p’ bits select the source addressing mode.

The ‘ccccc’ bits define the bit field LSb position within the target word.

The ‘mmmmm’ bits define the bit field MSb position within the target word.

If (condition) then {

If slit20 = 1 then skip next (16-bit) instruction

Else if (slit20 = 2 && next_op[31] = 1) then skip next (32-bit) instruction

Else (PC+4) + 2*slit20 → PC

}

Else no branch

If the 2’s complement byte offset value ‘2*slit20’ (the PC offset) equals two, the conditional branch will execute as a conditional skip of one 16-bit instruction. This instruction will be speculatively executed as not skipped until such time that the branch decision can be determined.

If the 2’s complement byte offset value ‘2*slit20’ (the PC offset) equals four and the instruction after the branch is a 32-bit opcode (see note), the conditional branch will execute as a conditional skip of that 32-bit instruction. This instruction will be speculatively executed as not skipped until such time that the branch decision can be determined.

If requirements for a conditional skip are not met, the 2’s complement byte offset value ‘2*slit20’ is added to the PC to create a new PS word address. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+4) + 2*slit20.

Branch prediction is based on the direction of the branch. If the branch is backwards (negative), it will be predicted as taken. If the branch is forwards (positive), it will be predicted as not taken. The two instructions that follow the branch will then be speculatively executed in the predicted path until such time that the actual branch decision can be assessed. A correctly predicted branch will continue instruction execution in the same path unabated. An incorrectly predicted branch will abort the speculatively executed instructions and start execution from the correct path.

The ‘n’ bits are a signed literal that specifies the number of PS words offset from (PC+4).

The taken branch target instruction fetch is not executed if an exception is pending, making effective instruction execution time one cycle.

If (condition) then {

If slit20 = 1 then skip next (16-bit) instruction

Else if (slit20 = 2 && next_op[31] = 1) then skip next (32-bit) instruction

Else (PC+4) + 2*slit20 → PC

}

Else no branch

If the 2’s complement byte offset value ‘2*slit20’ (the PC offset) equals two, the conditional branch will execute as a conditional skip of one 16-bit instruction. This instruction will be speculatively executed as not skipped until such time that the branch decision can be determined.

If the 2’s complement byte offset value ‘2*slit20’ (the PC offset) equals four and the instruction after the branch is a 32-bit opcode (see note), the conditional branch will execute as a conditional skip of that 32-bit instruction. This instruction will be speculatively executed as not skipped until such time that the branch decision can be determined.

If requirements for a conditional skip are not met, the 2’s complement byte offset value ‘2*slit20’ is added to the PC to create a new PS word address. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+4) + 2*slit20.

Branch prediction is based on the direction of the branch. If the branch is backwards (negative), it will be predicted as taken. If the branch is forwards (positive), it will be predicted as not taken. The two instructions that follow the branch will then be speculatively executed in the predicted path until such time that the actual branch decision can be assessed. A correctly predicted branch will continue instruction execution in the same path unabated. An incorrectly predicted branch will abort the speculatively executed instructions and start execution from the correct path.

The ‘n’ bits are a signed literal that specifies the number of PS words offset from (PC+4).

If (condition) then {

If slit20 = 1 then skip next (16-bit) instruction

Else if (slit20 = 2 && next_op[31] = 1) then skip next (32-bit) instruction

Else (PC+4) + 2*slit20 → PC

}

Else no branch

If the 2’s complement byte offset value ‘2*slit20’ (the PC offset) equals two, the conditional branch will execute as a conditional skip of one 16-bit instruction. This instruction will be speculatively executed as not skipped until such time that the branch decision can be determined.

If the 2’s complement byte offset value ‘2*slit20’ (the PC offset) equals four, and the instruction after the branch is a 32-bit opcode (see note), the conditional branch will execute as a conditional skip of that 32-bit instruction. This instruction will be speculatively executed as not skipped until such time that the branch decision can be determined.

If requirements for a conditional skip are not met, the 2’s complement byte offset value ‘2*slit20’ is added to the PC to create a new PS word address. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+4) + 2*slit20.

Branch prediction is based on the direction of the branch. If the branch is backwards (negative), it will be predicted as taken. If the branch is forwards (positive), it will be predicted as not taken. The two instructions that follow the branch will then be speculatively executed in the predicted path until such time that the actual branch decision can be assessed. A correctly predicted branch will continue instruction execution in the same path unabated. An incorrectly predicted branch will abort the speculatively executed instructions and start execution from the correct path.

The ‘n’ bits are a signed literal that specifies the number of PS words offset from (PC+4).

If (condition) then {

If slit20 = 1 then skip next (16-bit) instruction

Else if (slit20 = 2 && next_op[31] = 1) then skip next (32-bit) instruction

Else (PC+4) + 2*slit20 → PC

}

Else no branch

If the 2’s complement byte offset value ‘2*slit20’ (the PC offset) equals two, the conditional branch will execute as a conditional skip of one 16-bit instruction. This instruction will be speculatively executed as not skipped until such time that the branch decision can be determined.

If the 2’s complement byte offset value ‘2*slit20’ (the PC offset) equals four, and the instruction after the branch is a 32-bit opcode (see note), the conditional branch will execute as a conditional skip of that 32-bit instruction. This instruction will be speculatively executed as not skipped until such time that the branch decision can be determined.

If requirements for a conditional skip are not met, the 2’s complement byte offset value ‘2*slit20’ is added to the PC to create a new PS word address. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+4) + 2*slit20.

Branch prediction is based on the direction of the branch. If the branch is backwards (negative), it will be predicted as taken. If the branch is forwards (positive), it will be predicted as not taken. The two instructions that follow the branch will then be speculatively executed in the predicted path until such time that the actual branch decision can be assessed. A correctly predicted branch will continue instruction execution in the same path unabated. An incorrectly predicted branch will abort the speculatively executed instructions and start execution from the correct path.

The ‘n’ bits are a signed literal that specifies the number of PS words offset from (PC+4).

If (condition) then {

If slit20 = 1 then skip next (16-bit) instruction

Else if (slit20 = 2 && next_op[31] = 1) then skip next (32-bit) instruction

Else (PC+4) + 2*slit20 → PC

}

Else no branch

If the 2’s complement byte offset value ‘2*slit20’ (the PC offset) equals two, the conditional branch will execute as a conditional skip of one 16-bit instruction. This instruction will be speculatively executed as not skipped until such time that the branch decision can be determined.

If the 2’s complement byte offset value ‘2*slit20’ (the PC offset) equals four, and the instruction after the branch is a 32-bit opcode (see note), the conditional branch will execute as a conditional skip of that 32-bit instruction. This instruction will be speculatively executed as not skipped until such time that the branch decision can be determined.

If requirements for a conditional skip are not met, the 2’s complement byte offset value ‘2*slit20’ is added to the PC to create a new PS word address. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+4) + 2*slit20.

Branch prediction is based on the direction of the branch. If the branch is backwards (negative), it will be predicted as taken. If the branch is forwards (positive), it will be predicted as not taken. The two instructions that follow the branch will then be speculatively executed in the predicted path until such time that the actual branch decision can be assessed. A correctly predicted branch will continue instruction execution in the same path unabated. An incorrectly predicted branch will abort the speculatively executed instructions and start execution from the correct path.

The ‘n’ bits are a signed literal that specifies the number of PS words offset from (PC+4).