1.1.7 DSP Context Switch Support

DSP Overflow and Saturation Status bits are writable. This allows the state of the DSP engine to be efficiently saved and restored while switching between DSP tasks. See DSP ALU Status Bits for more details on DSP Status bits. There are also seven additional sets of CORCON, DSP Accumulators A and B for fast context switching; each set is inherently assigned to a respective IPL.

Any writes to CORCON at context-0 will be replicated across all DSP-related bits within CORCON registers mapped to contexts 1–7, until a write is made to the CORCON within one of the contexts 1–7 for the first time. A reset will re-enable CORCON write replication.

For instance, if the CPU IPL changes to IPL3 and the user writes to the associated CORCON (that is, CORCON of context-3), any subsequent writes to CORCON from context-0 will no longer affect CORCON from context-3. This applies to any CORCON register that was written from within its context. In contrast, further writes to CORCON at context-0 will continue to replicate over all CORCON registers that haven't been written to from within their contexts.

The code can assume that the DSP CORCON state remains consistent across all CPU register contexts following a reset and background initialization. In many applications, all DSP functions will utilize the same DSP engine configuration, making consistent initialization beneficial by eliminating the need to set up CORCON for each context individually. However, if a specific context requires a unique DSP engine configuration, it can initialize it as needed and subsequently prevent any background changes to CORCON from affecting the local CORCON configuration.