1.1.11 DSP Engine

The DSP engine features a high-speed 33-bit by 33-bit multiplier, a 72-bit ALU, two 72-bit saturating accumulators and a 72-bit bidirectional barrel shifter. The barrel shifter is capable of shifting a 72-bit value up to 32 bits right or up to 32 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two Working registers. This requires that the data space be split for these instructions and linear for all others. This is achieved in a transparent and flexible manner through dedicating certain Working registers to each address space.