1.1.4 Arithmetic and Logic Unit

A high-speed, 33-bit by 33-bit multiplier is included to significantly enhance the core’s arithmetic capability and throughput. The multiplier supports signed and unsigned, as well as 32-bit by 32-bit, or 16-bit by 16-bit integer multiplication. All multiply instructions execute in a single cycle.

The Arithmetic Logic Unit (ALU) is enhanced with integer divide assist hardware that supports an iterative non-restoring divide algorithm. It operates in conjunction with the REPEAT instruction looping mechanism and a selection of iterative divide instructions to support 32/32-bit, 32/16-bit, and 16/16-bit signed and unsigned, integer and fractional divide operations.