1.1 Features Specific to the dsPIC33A Core

The dsPIC33A devices are 32-bit (data) modified Harvard architecture, with a 5-stage instruction pipeline and a single-phase clock design, featuring an enhanced instructions set. The core has a 32-bit instruction word with an 8-bit opcode field. The Program Counter (PC) is 24 bits wide and addresses up to 4M x 32 bits of user program memory space. An instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. The majority of instructions execute in a single cycle.