35.4 Supply Voltage

Table 35-4. Supply Voltage
SymbolMin.Typ. ✝Max.UnitConditions
Supply Voltage(1)
VDD1.8(2)—5.5V
RAM Data Retention(3)
VDR1.7——VDevice in Power-Down mode
Power-on Reset Release Voltage(5)
VPOR—1.6—VBOD disabled(4)
tPOR———μsBOD disabled(4)
Power-on Reset Re-Arm Voltage(5)
VPORR———VBOD disabled(4)
tPORR———μsBOD disabled(4)
VDD Slope(6)
SVDD——0.5V/µs

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.

Note:
  1. During Chip Erase, the Brown-out Detector (BOD) configured with BODLEVEL0 is forced ON. The erase attempt will fail if the supply voltage VDD is below VBOD for BODLEVEL0.
  2. Operation is ensured down to 1.8V or BOD triggering level VBOD when BOD is active.
  3. This is the limit to which VDD can be lowered in sleep mode without losing RAM data.
  4. Refer to RSTCTRL and BOD for BOD trip point information.
  5. Refer to Figure 35-1.
  6. For design guidance only and not tested in production.
Figure 35-1. POR and POR Re-Arm with Slow Rising VDD
Note: When POR is low, the device is held in Reset.