2.2 Design Checklist
(Ask a Question)The following table lists the various checks that design engineers must take care while designing a system.
| Guideline | Yes/No | Remarks |
|---|---|---|
| Prerequisites | ||
| – See PolarFire SoC Datasheet. – See PolarFire SoC FPGA Packaging and Pin Descriptions User Guide. | — | — |
| Refer to the board-level schematics of PolarFire SoC Evaluation Kit | — | — |
| Device Selection | ||
| Check for available device variants for
PolarFire SoC FPGA – Select a device based on I/O pin count, transceivers, package, phase-locked loops (PLLs), and speed grade | — | — |
| Check device errata in PolarFire SoC FPGA Errata (yet to be published) | — | — |
| Design Checklist | ||
| Power Analysis Download the PolarFire and PolarFire SoC FPGA Power Estimator and check for the power budget. For more information, see UG0897: PolarFire and PolarFire SoC FPGA Power Estimator User Guide. | — | — |
| Power Supply Checklist See Power Supplies for used power rails. See Unused Power Supply and Figure 2 for unused rails. | — | — |
| Decoupling Capacitors Follow PolarFire SoC Decoupling Capacitors. Perform PI Analysis for any deviation from the recommended capacitors. | — | — |
| Clocks | ||
| For more information about dynamic phase
shift ports, see Table 6 of PolarFire FPGA and PolarFire SoC FPGA Clocking
Resources User Guide. The XCVR reference clock ranges from 20 MHz to 400 MHz. | — | — |
| The global clock network can be driven by any
of the following: – Preferred clock inputs (CLKIN_z_w) – On-chip oscillators – CCC (PLL/DLL) – XCVR interface clocks High-Speed I/O Clocks High-speed I/O clock networks can be driven by I/O or CCCs. The high-speed I/O clocks can feed reference clock inputs of adjacent CCCs through hardwired connections. CCC The CCC can be configured to have a PLL or DLL clock output, driving a high-speed I/O clock network. | — | — |
| Global buffer (GB) can be driven through the
dedicated global I/O, CCC or fabric (regular I/O) routing. The global network
is composed of GBs to distribute low-skew clock signals or high-fanout nets. Dedicated global I/O drive the GBs directly and are the primary source for connecting external clock inputs (to minimize the delay) to the internal global clock network. For more information about global clock network, see PolarFire FPGA and PolarFire SoC FPGA Clocking Resources User Guide. | — | — |
| Reset | ||
| For more information about DEVRST_N and user reset, see Reset. | — | — |
| DDR Interface | ||
| For more information about DDR routing and topology, see PolarFire FPGA and PolarFire SoC FPGA Memory Controller User Guide. | — | — |
| Programming and Debugging Scheme For programming and debugging information, see Device Programming. | — | — |
| XCVR | ||
| For more information about XCVR, see PolarFire FPGA and PolarFire SoC FPGA Transceiver User Guide. | — | — |
| For I/O gearing interfaces, place the clocks and data based on the defined requirements by selecting the correct I/O. For more information about the placement of User I/O, see PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide. | — | — |
| There is one IO_CFG_INTF pin available, which can be used as input. | — | — |
| See the bank location diagrams in the PolarFire SoC FPGA Packaging and Pin Descriptions User Guide to assess the preliminary placement of major components on PCB. | — | — |