14.2.1.3 Interrupt Handling
All interrupts provided by the AT86RF212B are supported in Basic Operating Mode. For example, interrupts are provided to observe the status of radio transceiver RX and TX operations.
When being in receive mode, IRQ_2 (RX_START) indicates the detection of a valid PHR first, IRQ_5 (AMI) an address match, and IRQ_3 (TRX_END) the completion of the frame reception. During transmission, IRQ_3 (TRX_END) indicates the completion of the frame transmission.
The figure below shows an example for a transmit/receive transaction between two devices and the related interrupt events in Basic Operating Mode. Device 1 transmits a frame containing a MAC header (in this example of length seven), MAC payload, and a valid FCS. The end of the frame transmission is indicated by IRQ_3 (TRX_END).
The frame is received by Device 2. Interrupt IRQ_2 (RX_START) indicates the detection of a valid PHR field and IRQ_3 (TRX_END) the completion of the frame reception. If the frame passes the Frame Filter, an address match interrupt IRQ_5 (AMI) is issued after the reception of the MAC header (MHR). The received frame is stored in the Frame Buffer.
In Basic Operating Mode the third interrupt IRQ_3 (TRX_END) is issued at the end of the received frame. In Extended Operating Mode the interrupt is only issued if the received frame passes the address filter and the FCS is valid.
Processing delay tIRQ is a typical value.
