13.25.8.3.5 Device EndPoint Interrupt Flag n


Bit	7	6	5	4	3	2	1	0
		STALL1	STALL0	RXSTP	TRFAIL1	TRFAIL0	TRCPT1	TRCPT0
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	2	0	0	2	0	2

Bits 5, 6 – STALL Transmit Stall x Interrupt Flag

This flag is cleared by writing a ‘1’ to the flag.

This flag is set when a Transmit Stall occurs and will generate an interrupt if EPINTENCLR/SET.STALL is ‘1’.

EPINTFLAG.STALL is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is ‘0’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the STALL Interrupt Flag.

Bit 4 – RXSTP Received Setup Interrupt Flag

This flag is cleared by writing a ‘1’ to the flag.

This flag is set when a Received Setup occurs and will generate an interrupt if EPINTENCLR/SET.RXSTP is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the RXSTP Interrupt Flag.

Bits 2, 3 – TRFAIL Transfer Fail x Interrupt Flag

This flag is cleared by writing a ‘1’ to the flag.

This flag is set when a transfer fail occurs and will generate an interrupt if EPINTENCLR/SET.TRFAIL is ‘1’.

EPINTFLAG.TRFAIL is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is ‘0’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the TRFAIL Interrupt Flag.

Bits 0, 1 – TRCPT Transfer Complete x Interrupt Flag

This flag is cleared by writing a ‘1’ to the flag.

This flag is set when a Transfer complete occurs and will generate an interrupt if EPINTENCLR/SET.TRCPT is ‘1’. EPINTFLAG.TRCPT is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is ‘0’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the TRCPT0 Interrupt Flag.

Name:	EPINTFLAGn
Offset:	0x107
Reset:	0x00
Property:	—