13.25.8.3.6 Device EndPoint Interrupt Enable n
| Name: | EPINTENCLRn |
| Offset: | 0x108 + (n x 0x20) |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 6 – STALL1 Transmit STALL 1 Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Stall 1 Interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Transmit Stall 1 interrupt is disabled. |
| 1 | The Transmit Stall 1 interrupt is enabled and an interrupt request will be generated when the Transmit Stall 1 Interrupt Flag is set. |
Bit 5 – STALL0 Transmit STALL 0 Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Stall 0 Interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Transmit Stall 0 interrupt is disabled. |
| 1 | The Transmit Stall 0 interrupt is enabled and an interrupt request will be generated when the Transmit Stall 0 Interrupt Flag is set. |
Bit 4 – RXSTP Received Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Received Setup Interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Received Setup interrupt is disabled. |
| 1 | The Received Setup interrupt is enabled and an interrupt request will be generated when the Received Setup Interrupt Flag is set. |
Bit 3 – TRFAIL1 Transfer Fail 1 Interrupt Enable
The user should look into the descriptor table status located in ram to be informed about the error condition : ERRORFLOW, CRC.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail 1 Interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Transfer Fail 1 interrupt is disabled. |
| 1 | The Transfer Fail 1 interrupt is enabled and an interrupt request will be generated when the Transfer Fail 1 Interrupt Flag is set. |
Bit 2 – TRFAIL0 Transfer Fail 0 Interrupt Enable
The user should look into the descriptor table status located in ram to be informed about the error condition : ERRORFLOW, CRC.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail 0 Interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Transfer Fail bank 0 interrupt is disabled. |
| 1 | The Transfer Fail bank 0 interrupt is enabled and an interrupt request will be generated when the Transfer Fail 0 Interrupt Flag is set. |
Bit 1 – TRCPT1 Transfer Complete 1 Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete 1 Interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Transfer Complete 1 interrupt is disabled. |
| 1 | The Transfer Complete 1 interrupt is enabled and an interrupt request will be generated when the Transfer Complete 1 Interrupt Flag is set. |
Bit 0 – TRCPT0 Transfer Complete 0 interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete 0 interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Transfer Complete bank 0 interrupt is disabled. |
| 1 | The Transfer Complete bank 0 interrupt is enabled and an interrupt request will be generated when the Transfer Complete 0 Interrupt Flag is set. |