13.26.5.3 Clocks

The CCL bus clock (CLK_CCL_APB) can be enabled and disabled in the power manager, and the default state of CLK_CCL_APB can be found in the Peripheral Clock Masking.

A generic clock (GCLK_CCL) is optionally required to clock the CCL. This clock must be configured and enabled in the Generic Clock Controller (GCLK) before using the sequential sub-module of CCL. GCLK_CCL is required when input events, a filter, an edge detector, or asequential sub-module is enabled. Refer to GCLK - Generic Clock Controller for details.

This generic clock is asynchronous to the user interface clock (CLK_CCL_APB).