13.27.8.6 Interrupt Enable Set
Name: | INTENSET |
Offset: | 0x05 |
Reset: | 0x00 |
Property: | PAC Write-Protection |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
WINMON | OVERRUN | RESRDY | |||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 0 | 0 |
Bit 2 – WINMON Window Monitor Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Window Monitor Interrupt bit, which enables the Window Monitor interrupt.
Value | Description |
---|---|
0 | The Window Monitor interrupt is disabled. |
1 | The Window Monitor interrupt is enabled. |
Bit 1 – OVERRUN Overrun Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Overrun Interrupt bit, which enables the Overrun interrupt.
Value | Description |
---|---|
0 | The Overrun interrupt is disabled. |
1 | The Overrun interrupt is enabled. |
Bit 0 – RESRDY Result Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Result Ready Interrupt bit, which enables the Result Ready interrupt.
Value | Description |
---|---|
0 | The Result Ready interrupt is disabled. |
1 | The Result Ready interrupt is enabled. |