13.27.8.10 Control C
| Name: | CTRLC |
| Offset: | 0x0A |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection, Write-Synchronized |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WINMODE[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RESSEL[1:0] | CORREN | FREERUN | LEFTADJ | DIFFMODE | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 10:8 – WINMODE[2:0] Window Monitor Mode
These bits enable and define the window monitor mode.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | No window mode (default) |
| 0x1 | MODE1 | RESULT > WINLT |
| 0x2 | MODE2 | RESULT < WINUT |
| 0x3 | MODE3 | WINLT < RESULT < WINUT |
| 0x4 | MODE4 | WINUT < RESULT < WINLT |
| 0x5 - 0x7 | Reserved |
Bits 5:4 – RESSEL[1:0] Conversion Result Resolution
These bits define whether the ADC completes the conversion 12-, 10- or 8-bit result resolution.
| Value | Name | Description |
|---|---|---|
| 0x0 | 12BIT | 12-bit result |
| 0x1 | 16BIT | For averaging mode output |
| 0x2 | 10BIT | 10-bit result |
| 0x3 | 8BIT | 8-bit result |
Bit 3 – CORREN Digital Correction Logic Enabled
| Value | Description |
|---|---|
| 0 | Disable the digital result correction. |
| 1 | Enable the digital result correction. The ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCORR and OFFSETCORR registers. Conversion time will be increased by 13 cycles according to the value in the Offset Correction Value bit group in the Offset Correction register. |
Bit 2 – FREERUN Free Running Mode
| Value | Description |
|---|---|
| 0 | The ADC run in single conversion mode. |
| 1 | The ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. |
Bit 1 – LEFTADJ Left-Adjusted Result
| Value | Description |
|---|---|
| 0 | The ADC conversion result is right-adjusted in the RESULT register. |
| 1 | The ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. Writing this bit to zero (default) will right-adjust the value in the RESULT register. |
Bit 0 – DIFFMODE Differential Mode
| Value | Description |
|---|---|
| 0 | The ADC is running in singled-ended mode. |
| 1 | The ADC is running in differential mode. In this mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. |