These bits select the input source for generating
the CRC, as shown in the table below. The selected source is locked until either the
CRC generation is completed or the CRC module is disabled. This means the CRCSRC
cannot be modified when the CRC operation is ongoing. The lock is signaled by the
CRCBUSY status bit. CRC generation complete is generated and signaled from the
selected source when used with the DMA channel.
Value | Name | Description |
---|
0x00 | NOACT | No action |
0x01 | IO | I/O interface |
0x02-0x1F | - | Reserved |
0x20 | CHN | DMA channel 0 |
0x21 | CHN | DMA channel 1 |
0x22 | CHN | DMA channel 2 |
0x23 | CHN | DMA channel 3 |
0x24 | CHN | DMA channel 4 |
0x25 | CHN | DMA channel 5 |
0x26 | CHN | DMA channel 6 |
0x27 | CHN | DMA channel 7 |
0x28 | CHN | DMA channel 8 |
0x29 | CHN | DMA channel 9 |
0x2A | CHN | DMA channel 10 |
0x2B | CHN | DMA channel 11 |
0x2C | CHN | DMA channel 12 |
0x2D | CHN | DMA channel 13 |
0x2E | CHN | DMA channel 14 |
0x2F | CHN | DMA channel 15 |
0x30 | CHN | DMA channel 16 |
0x31 | CHN | DMA channel 17 |
0x32 | CHN | DMA channel 18 |
0x33 | CHN | DMA channel 19 |
0x34 | CHN | DMA channel 20 |
0x35 | CHN | DMA channel 21 |
0x36 | CHN | DMA channel 22 |
0x37 | CHN | DMA channel 23 |
0x38 | CHN | DMA channel 24 |
0x39 | CHN | DMA channel 25 |
0x3A | CHN | DMA channel 26 |
0x3B | CHN | DMA channel 27 |
0x3C | CHN | DMA channel 28 |
0x3D | CHN | DMA channel 29 |
0x3E | CHN | DMA channel 30 |
0x3F | CHN | DMA channel 31 |