13.14.8.13 Pending Channels

Name: PENDCH
Offset: 0x2C
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 PENDCH15PENDCH14PENDCH13PENDCH12PENDCH11PENDCH10PENDCH9PENDCH8 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 PENDCH7PENDCH6PENDCH5PENDCH4PENDCH3PENDCH2PENDCH1PENDCH0 
Access RRRRRRRR 
Reset 00000000 

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – PENDCH Pending Channel n [n=15..0]

This bit is cleared when trigger execution defined by channel trigger action settings for DMA channel n is started, when a bus error for DMA channel n is detected or when DMA channel n is disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT.

This bit is set when a transfer is pending on DMA channel n.