13.14.8.12 Busy Channels

Name: BUSYCH
Offset: 0x28
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 BUSYCH15BUSYCH14BUSYCH13BUSYCH12BUSYCH11BUSYCH10BUSYCH9BUSYCH8 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 BUSYCH7BUSYCH6BUSYCH5BUSYCH4BUSYCH3BUSYCH2BUSYCH1BUSYCH0 
Access RRRRRRRR 
Reset 00000000 

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – BUSYCHn Busy Channel n [x=15..0]

This bit is cleared when the channel trigger action for DMA channel n is complete, when a bus error for DMA channel n is detected, or when DMA channel n is disabled.

This bit is set when DMA channel n starts a DMA transfer.