13.22.6.4.1.1 Slave DMA

When using the I²C slave with DMA, an address match will cause the address interrupt flag (INTFLAG.ADDRMATCH) to be raised. After the interrupt has been serviced, data transfer will be performed through DMA.

The I²C slave generates the following requests:

Write data received (RX): The request is set when master write data is received. The request is cleared when DATA is read.
Read data needed for transmit (TX): The request is set when data is needed for a master read operation. The request is cleared when DATA is written.

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