11.3.7 Synchronization Delay

The synchronization will delay the read/write access duration by a delay D, as shown in the equation below:

5 \cdot P_{GCLK} + 2 \cdot P_{APB} < D < 6 \cdot P_{GCLK} + 3 \cdot P_{APB}

Where:

$P_{GCLK}$ is the period of the generic clock and $P_{APB}$ is the period of the peripheral bus clock. A normal peripheral bus register access duration is $2 \cdot P_{APB}$ .

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