28.6.5 Interrupt Flag Status and Clear
| Name: | INTFLAG |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | – |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| EVD5 | EVD4 | EVD3 | EVD2 | EVD1 | EVD0 | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVR5 | OVR4 | OVR3 | OVR2 | OVR1 | OVR0 | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 16, 17, 18, 19, 20, 21 – EVDx Event Detected Channel x [x = 5..0]
This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an interrupt request will be generated if INTENSET.EVDx is '1'.
When the event channel path is asynchronous, the EVDx interrupt flag will not be set.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Event Detected Channel x interrupt flag.
Bits 0, 1, 2, 3, 4, 5 – OVRx Overrun Channel x [x = 5..0]
This flag is set on the next CLK_EVSYS_APB cycle after an overrun channel condition occurs, and an interrupt request will be generated if INTENSET.OVRx is '1'.
- One or more of the event users on channel x are not ready when a new event occurs
- An event happens when the previous event on channel x has not yet been handled by all event users
When the event channel path is asynchronous, the OVRx interrupt flag will not be set.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Overrun Detected Channel x interrupt flag.