31.5.4.1.2 Software Configuration

• Assign EBI_CS1 to the MPDDRC controller by setting the EBI_CS1A bit in the SFR_CCFG_EBICSA register.
• Initialize the MPDDR Controller depending on the DDR2 device and system bus frequency.

The DDR2 initialization sequence is described in 32.4.3 DDR2-SDRAM Initialization.

In this case, VDDNF can be different from VDDIOM. The NAND Flash device can be 3.3V or 1.8V and wired on the D[23:16] data bus. NFD0_ON_D16 is to be set to 1.