The flowcharts shown in this section provide examples for read and
write operations. A polling or interrupt method can be used to check the status bits. The
interrupt method requires that the Interrupt Enable register (FLEX_TWI_IER) be configured
first.
Figure 46-105. TWI Write Operation with Single Data Byte without Internal
AddressFigure 46-106. TWI Write Operation with Single Data Byte and Internal
AddressFigure 46-107. TWI Write Operation with Multiple Data Bytes with or without
Internal AddressFigure 46-108. SMBus Write Operation with Multiple Data Bytes with or
without Internal Address and PEC SendingFigure 46-109. SMBus Write Operation with Multiple Data Bytes with PEC and
Alternative Command ModeFigure 46-110. TWI Write Operation with Multiple Data Bytes and Read
Operation with Multiple Data Bytes (Sr)Figure 46-111. TWI Write Operation with Multiple Data Bytes + Read Operation
and Alternative Command Mode + PECFigure 46-112. TWI Read Operation with Single Data Byte without Internal
AddressFigure 46-113. TWI Read Operation with Single Data Byte and Internal
AddressFigure 46-114. TWI Read Operation with Multiple Data Bytes with or without
Internal AddressFigure 46-115. TWI Read Operation with Multiple Data Bytes with or without
Internal Address with PECFigure 46-116. TWI Read Operation with Multiple Data Bytes with Alternative
Command Mode with PECFigure 46-117. TWI Read Operation with Multiple Data Bytes + Write Operation
with Multiple Data Bytes (Sr)Figure 46-118. TWI Read Operation with Multiple Data Bytes + Write with
Alternative Command Mode with PEC
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