31.5.4.5.2 Software Configuration

The following configuration has to be performed:

• Set NFD0_ON_D16 = 0 in the SFR_CCFG_EBICSA register
• Assign the EBI CS3 to the NAND Flash by setting the EBI_CS3A bit in the SFR_CCFG_EBICSA register
• Reserve A21/A22 for ALE/CLE functions. Address and Command Latches are controlled respectively by setting to 1 the address bits A21 and A22 during accesses.
• Configure a PIO line as an input to manage the Ready/Busy signal.
• Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode according to NAND Flash timings, data bus width and system bus frequency.