52.7.13 PWM Channel Update Register x
| Name: | PWM_CUPDx |
| Offset: | 0x0210 + x*0x20 [x=0..3] |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CUPD[31:24] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CUPD[23:16] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CUPD[15:8] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CUPD[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
Bits 31:0 – CUPD[31:0] Channel Update Register
This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty cycle.
Only the first 16 bits (internal channel counter size) are significant.
When PWM_CMRx.CPD = 0, the duty cycle (CDTY of PWM_CDTYx) is updated with the CUPD value at the beginning of the next period.
When PWM_CMRx.CPD = 1, the period (CPRD of PWM_CPRDx) is updated with the CUPD value at the beginning of the next period.