52.7.1 PWM Mode Register
| Name: | PWM_MR |
| Offset: | 0x00 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PREB[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DIVB[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PREA[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIVA[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 27:24 – PREB[3:0] CLKB Source Clock Selection
| Value | Name | Description |
|---|---|---|
| 0000 | MCK | Peripheral clock |
| 0001 | MCKDIV2 | Peripheral clock divided by 2 |
| 0010 | MCKDIV4 | Peripheral clock divided by 4 |
| 0011 | MCKDIV8 | Peripheral clock divided by 8 |
| 0100 | MCKDIV16 | Peripheral clock divided by 16 |
| 0101 | MCKDIV32 | Peripheral clock divided by 32 |
| 0110 | MCKDIV64 | Peripheral clock divided by 64 |
| 0111 | MCKDIV128 | Peripheral clock divided by 128 |
| 1000 | MCKDIV256 | Peripheral clock divided by 256 |
| 1001 | MCKDIV512 | Peripheral clock divided by 512 |
| 1010 | MCKDIV1024 | Peripheral clock divided by 1024 |
| Other | – | Reserved |
Bits 23:16 – DIVB[7:0] CLKB Divide Factor
| Value | Name | Description |
|---|---|---|
| 0 | CLK_OFF |
The CLKB internal source clock is turned off. The PWMx output is stuck when PWM_CMRx.CPRE=CLKB. |
| 1 | CLK_DIV1 | CLKB is the clock selected by PREB. |
| 2–255 | – | CLKB is the clock selected by PREB, divided by the DIVB factor. |
Bits 11:8 – PREA[3:0] CLKA Source Clock Selection
| Value | Name | Description |
|---|---|---|
| 0000 | MCK | Peripheral clock |
| 0001 | MCKDIV2 | Peripheral clock divided by 2 |
| 0010 | MCKDIV4 | Peripheral clock divided by 4 |
| 0011 | MCKDIV8 | Peripheral clock divided by 8 |
| 0100 | MCKDIV16 | Peripheral clock divided by 16 |
| 0101 | MCKDIV32 | Peripheral clock divided by 32 |
| 0110 | MCKDIV64 | Peripheral clock divided by 64 |
| 0111 | MCKDIV128 | Peripheral clock divided by 128 |
| 1000 | MCKDIV256 | Peripheral clock divided by 256 |
| 1001 | MCKDIV512 | Peripheral clock divided by 512 |
| 1010 | MCKDIV1024 | Peripheral clock divided by 1024 |
| Other | – | Reserved |
Bits 7:0 – DIVA[7:0] CLKA Divide Factor
| Value | Name | Description |
|---|---|---|
| 0 | CLK_OFF |
The CLKA internal source clock is turned off. The PWMx output is stuck when PWM_CMRx.CPRE=CLKA. |
| 1 | CLK_DIV1 | CLKA is the clock selected by PREA. |
| 2–255 | – | CLKA is the clock selected by PREA, divided by the DIVA factor. |