52.7.8 PWM Interrupt Status Register
Note: Reading PWM_ISR automatically clears
the CHIDx flags.
| Name: | PWM_ISR |
| Offset: | 0x1C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHID3 | CHID2 | CHID1 | CHID0 | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3 – CHIDx Channel ID
| Value | Description |
|---|---|
| 0 | No new channel period has been achieved since the last read of PWM_ISR. |
| 1 | At least one new channel period has been achieved since the last read of PWM_ISR. |