52.7.9 PWM Channel Mode Register x
| Name: | PWM_CMRx |
| Offset: | 0x0200 + x*0x20 [x=0..3] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CPD | CPOL | CALG | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CPRE[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 10 – CPD Channel Update Period
| Value | Description |
|---|---|
| 0 | Writing to PWM_CUPDx will modify the duty cycle at the next period start event. |
| 1 | Writing to PWM_CUPDx will modify the period at the next period start event. |
Bit 9 – CPOL Channel Polarity
| Value | Description |
|---|---|
| 0 | The output waveform starts at a low level. |
| 1 | The output waveform starts at a high level. |
Bit 8 – CALG Channel Alignment
| Value | Description |
|---|---|
| 0 | The period is left-aligned. |
| 1 | The period is center-aligned. |
Bits 3:0 – CPRE[3:0] Channel Prescaler
| Value | Name | Description |
|---|---|---|
| 0000 | MCK | Peripheral clock |
| 0001 | MCKDIV2 | Peripheral clock divided by 2 |
| 0010 | MCKDIV4 | Peripheral clock divided by 4 |
| 0011 | MCKDIV8 | Peripheral clock divided by 8 |
| 0100 | MCKDIV16 | Peripheral clock divided by 16 |
| 0101 | MCKDIV32 | Peripheral clock divided by 32 |
| 0110 | MCKDIV64 | Peripheral clock divided by 64 |
| 0111 | MCKDIV128 | Peripheral clock divided by 128 |
| 1000 | MCKDIV256 | Peripheral clock divided by 256 |
| 1001 | MCKDIV512 | Peripheral clock divided by 512 |
| 1010 | MCKDIV1024 | Peripheral clock divided by 1024 |
| 1011 | CLKA | Clock A |
| 1100 | CLKB | Clock B |
| Other | – | Reserved |