49.6 Register Summary

Note: Several parts of the ISI controller use the pixel clock provided by the image sensor (ISI_PCK). Thus the user must first program the image sensor to provide this clock (ISI_PCK) before programming the Image Sensor Controller.


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	ISI_CFG1	31:24	SFD[7:0]
		23:16	SLD[7:0]
		15:8		THMASK[1:0]		FULL	DISCR	FRATE[2:0]
		7:0	CRC_SYNC	EMB_SYNC	GRAYLE	PIXCLK_POL	VSYNC_POL	HSYNC_POL
0x04	ISI_CFG2	31:24	RGB_CFG[1:0]		YCC_SWAP[1:0]			IM_HSIZE[10:8]
		23:16	IM_HSIZE[7:0]
		15:8	COL_SPACE	RGB_SWAP	GRAYSCALE	RGB_MODE	GS_MODE	IM_VSIZE[10:8]
		7:0	IM_VSIZE[7:0]
0x08	ISI_PSIZE	31:24							PREV_HSIZE[9:8]
		23:16	PREV_HSIZE[7:0]
		15:8							PREV_VSIZE[9:8]
		7:0	PREV_VSIZE[7:0]
0x0C	ISI_PDECF	31:24
		23:16
		15:8
		7:0	DEC_FACTOR[7:0]
0x10	ISI_Y2R_SET0	31:24	C3[7:0]
		23:16	C2[7:0]
		15:8	C1[7:0]
		7:0	C0[7:0]
0x14	ISI_Y2R_SET1	31:24
		23:16
		15:8		Cboff	Croff	Yoff				C4[8]
		7:0	C4[7:0]
0x18	ISI_R2Y_SET0	31:24								Roff
		23:16		C2[6:0]
		15:8		C1[6:0]
		7:0		C0[6:0]
0x1C	ISI_R2Y_SET1	31:24								Goff
		23:16		C5[6:0]
		15:8		C4[6:0]
		7:0		C3[6:0]
0x20	ISI_R2Y_SET2	31:24								Boff
		23:16		C8[6:0]
		15:8		C7[6:0]
		7:0		C6[6:0]
0x24	ISI_CR	31:24
		23:16
		15:8								ISI_CDC
		7:0						ISI_SRST	ISI_DIS	ISI_EN
0x28	ISI_SR	31:24					FR_OVR	CRC_ERR	C_OVR	P_OVR
		23:16					SIP		CXFR_DONE	PXFR_DONE
		15:8						VSYNC		CDC_PND
		7:0						SRST	DIS_DONE	ENABLE
0x2C	ISI_IER	31:24					FR_OVR	CRC_ERR	C_OVR	P_OVR
		23:16							CXFR_DONE	PXFR_DONE
		15:8						VSYNC
		7:0						SRST	DIS_DONE
0x30	ISI_IDR	31:24					FR_OVR	CRC_ERR	C_OVR	P_OVR
		23:16							CXFR_DONE	PXFR_DONE
		15:8						VSYNC
		7:0						SRST	DIS_DONE
0x34	ISI_IMR	31:24					FR_OVR	CRC_ERR	C_OVR	P_OVR
		23:16							CXFR_DONE	PXFR_DONE
		15:8						VSYNC
		7:0						SRST	DIS_DONE
0x38	ISI_DMA_CHER	31:24
		23:16
		15:8
		7:0							C_CH_EN	P_CH_EN
0x3C	ISI_DMA_CHDR	31:24
		23:16
		15:8
		7:0							C_CH_DIS	P_CH_DIS
0x40	ISI_DMA_CHSR	31:24
		23:16
		15:8
		7:0							C_CH_S	P_CH_S
0x44	ISI_DMA_P_ADDR	31:24	P_ADDR[29:22]
		23:16	P_ADDR[21:14]
		15:8	P_ADDR[13:6]
		7:0	P_ADDR[5:0]
0x48	ISI_DMA_P_CTRL	31:24
		23:16
		15:8
		7:0					P_DONE	P_IEN	P_WB	P_FETCH
0x4C	ISI_DMA_P_DSCR	31:24	P_DSCR[29:22]
		23:16	P_DSCR[21:14]
		15:8	P_DSCR[13:6]
		7:0	P_DSCR[5:0]
0x50	ISI_DMA_C_ADDR	31:24	C_ADDR[29:22]
		23:16	C_ADDR[21:14]
		15:8	C_ADDR[13:6]
		7:0	C_ADDR[5:0]
0x54	ISI_DMA_C_CTRL	31:24
		23:16
		15:8
		7:0					C_DONE	C_IEN	C_WB	C_FETCH
0x58	ISI_DMA_C_DSCR	31:24	C_DSCR[29:22]
		23:16	C_DSCR[21:14]
		15:8	C_DSCR[13:6]
		7:0	C_DSCR[5:0]
0x5C ... 0xE3	Reserved
0xE4	ISI_WPMR	31:24	WPKEY[23:16]
		23:16	WPKEY[15:8]
		15:8	WPKEY[7:0]
		7:0								WPEN
0xE8	ISI_WPSR	31:24
		23:16	WPVSRC[15:8]
		15:8	WPVSRC[7:0]
		7:0								WPVS