26.9.4 AIC Interrupt Vector Register
| Name: | AIC_IVR |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| IRQV[31:24] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| IRQV[23:16] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| IRQV[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IRQV[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – IRQV[31:0] Interrupt Vector Register
Contains the vector programmed by the user in AIC_SVR or the interrupt index corresponding to the current interrupt. (See the sections AIC_SVRRER, AIC_SVRRDR and AIX_SVRRSR.)
AIC_SVR is indexed using the current interrupt number when AIC_IVR is read.
When there is no current interrupt, AIC_IVR reads the value stored in AIC_SPU.