50.8.4.2.3 Freezing the Internal Timer Counter

The internal counter can be frozen by setting CAN_MR.TIMFRZ. This prevents an unexpected roll-over when the counter reaches FFFFh. When this occurs, it automatically freezes until a new reset is issued, either due to a message received in the last mailbox or any other reset counter operations. The CAN_SR.TOVF bit is set when the counter is frozen. TOVF is cleared by reading CAN_SR. Depending on the corresponding interrupt mask in CAN_IMR, an interrupt is generated when TOVF is set.