31.5.4.4.2 Software Configuration

The following configuration must be performed:

• Assign the EBI CS1 to the SDRAM controller by setting the EBI_CS1A bit in the SFR_CCFG_EBICSA register.
• Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.

Program the Data Bus Width to 32 bits. The data lines D[16:31] are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in Peripheral mode in the PIO controller.

The SDRAM initialization sequence is described in the section “SDRAM Device Initialization” in “SDRAM Controller (SDRAMC)”.

In this case, VDDNF must be equal to VDDIOM. The NAND Flash device must be 3.3V and wired on the D[7:0] data bus. NFD0_ON_D16 is to be set to 0.