31.5.4.2.2 Software Configuration

The following configuration must be performed:

• Assign EBI_CS1 to the MPDDR controller by setting the bit EBI_CS1A bit in the SFR_CCFG_EBICSA register.
• Initialize the MPDDR Controller depending on the LP-DDR device and system bus frequency.

The LP-DDR initialization sequence is described in the section “Low-power DDR1-SDRAM Initialization” in the MPDDRC section.

In this case, VDDNF can be different from VDDIOM. The NAND Flash device can be 3.3V or 1.8V and wired on the D[23:16] data bus. NFD0_ON_D16 is to be set to 1.