5 Device Operation
The AT25128B/AT25256B is controlled by a set of instructions sent from a host controller, commonly referred to as the SPI Host. The SPI Host communicates with the AT25128B/AT25256B via the SPI bus, which comprises four signal lines: Chip Select (CS), Serial Data Clock (SCK), Serial Data Input (SI) and Serial Data Output (SO).
The SPI protocol defines a total of four modes of operation (Mode 0, 1, 2 or 3) with each mode differing in terms of SCK polarity and phase, which control the flow of data on the SPI bus. The AT25128B/AT25256B supports the two most common modes, SPI Modes 0 and 3. With SPI Modes 0 and 3, data are always latched in on the rising edge of SCK and always output on the falling edge of SCK. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the Inactive state (when the SPI Host is in Standby mode and not transferring any data). SPI Mode 0 is defined as having a low SCK while CS is not asserted (at VCC), and SPI Mode 3 has SCK high in the Inactive state. The SCK Idle state must match when the CS is deasserted both before and after the communication sequence in SPI Modes 0 and 3. The figures in this document depict Mode 0 with a solid line on SCK while CS is inactive and Mode 3 with a dotted line.