2.2 Design Steps

Select R2: The lower feedback resistor R2 is selected in the kΩ range to limit the feedback divider bias current.

For this design example, R2 = 3 kΩ is selected, considering V_REF = 0.6V and approximately 200 μA bias current.

Calculate R1: Once R2 is selected, R1 is calculated based on the required output voltage using:

Equation 2-1.

R 1 = R 2 \cdot (\frac{V_{OUT}}{V_{REF}} - 1)

For V_OUT = 5V, the calculated value is: R1 = 22 kΩ

Choose F_C: The crossover frequency is selected between F_SW/10 and F_SW/20. Since F_SW = 266 kHz, a crossover frequency of F_C = 20 kHz is chosen.

Calculate ΔV_FB: The feedback ripple must be within 40 mV to 200 mV, unless otherwise specified in the data sheet. It is estimated using:

Equation 2-2.

∆ V_{FB} = \frac{V_{O} \cdot (1 - D)}{2 π \cdot L \cdot C_{OUT} \cdot F_{C} \cdot F_{SW}}

For this design, the initial calculated feedback ripple is: ΔV_FB = 130 mV. This value must be recalculated after selecting C_FF and R_INJ.

Calculate C_FF: The feed-forward capacitor is selected to place the second zero slightly below F_C.

In this example, F_Z2 is placed at $F_{C} / \sqrt{3}$ , providing sufficient phase boost at crossover. So, C_FF can be calculated using:

Equation 2-3.

C_{FF} = \frac{\sqrt{3}}{2 π \cdot R 1 \cdot F_{C}}

The calculated value is approximately: C_FF = 630 pF. For testing, the value selected is: C_FF = 560 pF.

Calculate R_INJ: The ripple injection resistor is calculated using rearranged Equation 1-20 as:

Equation 2-4.

R_{INJ} = \frac{V_{O} \cdot (1 - D)}{{ΔV}_{FB} \cdot C_{FF} \cdot F_{SW}}

The calculated value is approximately: R_INJ = 230 kΩ. For practical implementation and testing, the standard value selected in this example is: R_INJ = 200 kΩ.

Recalculate Feedback Ripple (ΔV_FB): After selecting practical component values for C_FF and R_INJ, it is important to recalculate the resulting feedback ripple to account for deviations from the ideal calculated values.

For C_FF = 560 pF and R_INJ = 200 kΩ, the recalculated feedback ripple is: ΔV_FB = 150 mV.

It is essential to verify that this final value lies within the recommended operating range specified for the device. Ensuring that the feedback ripple remains within this range is critical for maintaining proper comparator operation, avoiding noise sensitivity or jitter, and achieving stable and predictable control loop performance.

Calculate F_LC and C_INJ: The LC resonant frequency is calculated first using Equation 1-20. For this design: F_LC = 5 kHz. The DC blocking capacitor C_INJ is then selected to place the first zero 1-2 decades below F_LC.

In this example, first zero is placed two decades below F_LC. So C_INJ can be calculated using:

Equation 2-5.

C_{INJ} = \frac{10^{2}}{2 π \cdot R_{INJ} \cdot F_{LC}}

The calculated value is: C_INJ = 15.9 nF. For testing, the selected value is: C_INJ = 15 nF.

Verify Stability Criteria: The final step is to ensure we meet the required stability criteria. The impedance of C_FF at the switching frequency should be much smaller than the equivalent feedback resistance (R1‖R2), so that the current through the feedback resistors can be neglected, allowing the feed-forward capacitor to effectively couple the switching ripple to the feedback node. This can be verified using:

Equation 2-6.

\frac{1}{2 π \cdot C_{FF} \cdot F_{SW}} ≪ R 1 ∥ R 2

For the selected values: 1.06 kΩ < 2.64 kΩ. This confirms that the stability criterion is satisfied. Therefore, the ACOT control loop design is complete. However, final validation must always be performed on the bench to confirm feedback ripple, phase margin, and transient response.