17.7.3 Generator Control (GENCTRL0,2,3,4,5,6,7)

GENCTRLn controls the settings of Generic Generator n (n=0,2,3,4,5,6,7) (PIC32CM2532 and PIC32CM5164 devices).

GENCTRLn controls the settings of Generic Generator n (n=0,2,3,4) (PIC32CM1216 devices).

Important: GENCTRL1 has its own register described in GENCTRL1 register.

A User Reset will reset the associated GENCTRLn registers unless the Generator is the source of a locked Peripheral Channel m (PCHCTRLm.WRTLOCK=1).

Note: GENCTRLn is a write-synchronized register: SYNCBUSY.GENCTRLn must be checked to ensure the GENCTRLn synchronization is complete.

Name:	GENCTRLn
Offset:	0x20,0x28,0x2C,0x30,0x34,0x38,0x3C
Reset:	0x00000105 (GENCTRL0), 0x00000000 (others)
Property:	PAC Write-Protection, Write-Synchronized


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	DIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	x


Bit	7	6	5	4	3	2	1	0
					SRC[3:0]
Access					R/W	R/W	R/W	R/W
Reset					x	x	x	x

Bits 23:16 – DIV[7:0] Division Factor

These bits represent a division value for the corresponding Generator. The actual division factor is dependent on the state of DIVSEL.

Bit 13 – RUNSTDBY Run in Standby

This bit is used to keep the Generator running in Standby as long as it is configured to output to a dedicated GCLK_IO[n] pin. If GENCTRLn.OE is zero, this bit has no effect and the generator will only be running if a peripheral requires the clock.

Value	Description
0	The Generator is stopped in Standby and the GCLK_IO[n] pin state (one or zero) will be dependent on the setting in GENCTRL.OOV.
1	The Generator is kept running and output to its dedicated GCLK_IO[n] pin during Standby mode.

Bit 12 – DIVSEL Divide Selection

This bit determines how the division factor of the clock source of the Generator will be calculated from DIV. If the clock source should not be divided, DIVSEL must be 0 and the GENCTRLn.DIV value must be either 0 or 1.

Value	Description
0	The Generator clock frequency equals the clock source frequency divided by GENCTRLn.DIV.
1	The Generator clock frequency equals the clock source frequency divided by 2^(GENCTRLn.DIV + 1).

Bit 11 – OE Output Enable

This bit is used to output the Generator clock output to the corresponding pin (GCLK_IO[n]), as long as GCLK_IO[n] is not defined as the Generator source in the GENCTRLn.SRC bit field.

Value	Description
0	No Generator clock signal on pin GCLK_IO[n].
1	The Generator clock signal is output on the corresponding GCLK_IO[n], unless GCLK_IO[n] is selected as a generator source in the GENCTRLn.SRC bit field.

Bit 10 – OOV Output Off Value

This bit is used to control the clock output value on pin (GCLK_IO[n]) when the Generator is turned off or the OE bit is zero, as long as GCLK_IO[n] is not defined as the Generator source in the GENCTRLn.SRC bit field.

Value	Description
0	The GCLK_IO[n] will be LOW when generator is turned off or when the OE bit is zero.
1	The GCLK_IO[n] will be HIGH when generator is turned off or when the OE bit is zero.

Bit 9 – IDC Improve Duty Cycle

This bit is used to improve the duty cycle of the Generator output to 50/50 for odd division factors.

Value	Description
0	Generator output clock duty cycle is not balanced to 50/50 for odd division factors.
1	Generator output clock duty cycle is 50/50.

Bit 8 – GENEN Generator Enable

This bit is used to enable and disable the Generator.

Value	Description
0	Generator is disabled.
1	Generator is enabled.

Bits 3:0 – SRC[3:0] Generator Clock Source Selection

These bits select the Generator clock source, as shown in this table.

Table 17-4. Generator Clock Source Selection
Value	Name	Description
0x00	XOSC	XOSC oscillator output
0x01	GCLK_IN	Generator input pad (GCLK_IO[n])
0x02	GCLK_GEN1	Generic clock generator 1 output
0x03	OSCULP32K	OSCULP32K oscillator output
0x04	XOSC32K	XOSC32K oscillator output
0x05	OSC16M	OSC16M oscillator output
0x06	DFLLULP	DFLLULP ultra low power output
0x07	DFLL48M	DFLL48M output
0x08	FDPLL96M	FDPLL96M output
0x09-0x0F	Reserved	Reserved for future use