17.7.5 Peripheral Channel Control


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	WRTLOCK	CHEN				GEN[2:0]
Access	R/W	R/W				R/W	R/W	R/W
Reset	0	0				0	0	0

Bit 7 – WRTLOCK Write Lock

After this bit is set to '1', further writes to the PCHCTRLm register will be discarded. The control register of the corresponding Generator n (GENCTRLn), as assigned in PCHCTRLm.GEN, will also be locked. It can only be unlocked by a Power Reset.

Note that Generator 0 cannot be locked.

Value	Description
0	The Peripheral Channel register and the associated Generator register are not locked
1	The Peripheral Channel register and the associated Generator register are locked

Bit 6 – CHEN Channel Enable

This bit is used to enable and disable a Peripheral Channel.

CAUTION: This bit requires synchronization. When changing it, the bit value must be read-back (polling method) to ensure the synchronization is complete. Changing the bit value under ongoing synchronization will not generate an error.

Value	Description
0	The Peripheral Channel is disabled
1	The Peripheral Channel is enabled

Bits 2:0 – GEN[2:0] Generator Selection

This bit field selects the Generator to be used as the source of a peripheral clock, as shown in the table below:

Table 17-6. Generator Selection
Value	Description
0x0	Generic Clock Generator 0
0x1	Generic Clock Generator 1
0x2	Generic Clock Generator 2
0x3	Generic Clock Generator 3
0x4	Generic Clock Generator 4
0x5	Generic Clock Generator 5
0x6	Generic Clock Generator 6
0x7	Generic Clock Generator 7

A Power Reset will reset all the PCHCTRLm registers.

A User Reset will reset a PCHCTRL if WRTLOCK=0, or else, the content of that PCHCTRL remains unchanged.

Table 17-7. Reset Value after a User Reset or a Power Reset
Reset	PCHCTRLm.GEN	PCHCTRLm.CHEN	PCHCTRLm.WRTLOCK
Power Reset	0x0	0x0	0x0
User Reset	If WRTLOCK = 0 : 0x0 If WRTLOCK = 1: no change	If WRTLOCK = 0 : 0x0 If WRTLOCK = 1: no change	No change

The PCHCTRLm registers index values are shown in the following table :

Important: Refer to the Configuration Summary for the list of peripherals and peripheral instances present in each variant.

Table 17-8. PCHCTRLm Mapping
index(m)	Name	Description
0	GCLK_FDPLL96M	FDPLL96M input clock source for reference
1	GCLK_FDPLL96M_32K	FDPLL96M slow clock for FDPLL96M internal clock timer
2	GCLK_DFLLULP	DFLLULP clock for DFLLULP
3	GCLK_DFLL48M	DFLL48M clock for DFLL48M
4	GCLK_EIC	EIC
5	GCLK_FREQM_MSR	FREQM Measure
6	GCLK_FREQM_REF	FREQM Reference
7	GCLK_USB	USB
8	GCLK_EVSYS_CHANNEL_0	EVSYS_CHANNEL_0
9	GCLK_EVSYS_CHANNEL_1	EVSYS_CHANNEL_1
10	GCLK_EVSYS_CHANNEL_2	EVSYS_CHANNEL_2
11	GCLK_EVSYS_CHANNEL_3	EVSYS_CHANNEL_3
12	GCLK_EVSYS_CHANNEL_4	EVSYS_CHANNEL_4
13	GCLK_EVSYS_CHANNEL_5	EVSYS_CHANNEL_5
14	GCLK_EVSYS_CHANNEL_6	EVSYS_CHANNEL_6
15	GCLK_EVSYS_CHANNEL_7	EVSYS_CHANNEL_7
16	GCLK_SERCOM0_SLOW GCLK_SERCOM1_SLOW GCLK_SERCOM2_SLOW GCLK_SERCOM3_SLOW GCLK_SERCOM4_SLOW GCLK_SERCOM5_SLOW	SERCOM0_SLOW SERCOM1_SLOW SERCOM2_SLOW SERCOM3_SLOW SERCOM4_SLOW SERCOM5_SLOW
17	GCLK_SERCOM0_CORE	SERCOM0_CORE
18	GCLK_SERCOM1_CORE	SERCOM1_CORE
19	GCLK_SERCOM2_CORE	SERCOM2_CORE
20	GCLK_SERCOM3_CORE	SERCOM3_CORE
21	GCLK_SERCOM4_CORE	SERCOM4_CORE
22	GCLK_SERCOM5_CORE	SERCOM5_CORE
23	GCLK_TC0_TC1	TC0,TC1
24	GCLK_TC2	TC2
25	GCLK_TCC0_TCC1	TCC0,TCC1
26	GCLK_TCC2	TCC2
27	GCLK_TCC3	TCC3
28	GCLK_ADC	ADC
29	GCLK_AC	AC
30	GCLK_DAC	DAC
31	GCLK_PTC	PTC
32	GCLK_CCL	CCL
33	GCLK_I2S_0	I2S Clock Unit 0
34	GCLK_I2S_1	I2S Clock Unit 1

Name:	PCHCTRLm
Offset:	0x80 + m*0x04 [m=0..34]
Reset:	0x00000000
Property:	PAC Write-Protection