42.6.2.7 Sequential Logic

Each LUT pair can be connected to the internal sequential logic which can be configured to work as D flip flop, JK flip flop, gated D-latch or RS-latch by writing the Sequential Selection bits on the corresponding Sequential Control x register (SEQCTRLx.SEQSEL). Before using sequential logic, the GCLK_CCL clock and optionally each LUT filter or edge detector must be enabled.

Gated D Flip-Flop (DFF)

When the DFF is selected, the D-input is driven by the even LUT output (LUT(2n)), and the G-input is driven by the odd LUT output (LUT(2n+1)), as shown in Figure 42-14.

When the even LUT is disabled (LUTCTRL(2n).ENABLE=0), the flip-flop is asynchronously cleared. The reset command (R) is kept enabled for one APB clock cycle. In all other cases, the flip-flop output (OUT) is refreshed on rising edge of the GCLK_CCL, as shown in Table 42-3.

JK Flip-Flop (JK)

When this configuration is selected, the J-input is driven by the even LUT output (LUT(2n)), and the K-input is driven by the odd LUT output (LUT(2n+1)), as shown in Figure 42-15.

When the even LUT is disabled (LUTCTRL(2n).ENABLE=0), the flip-flop is asynchronously cleared. The reset command (R) is kept enabled for one APB clock cycle. In all other cases, the flip-flop output (OUT) is refreshed on rising edge of the GCLK_CCL, as shown in Table 42-4.

Gated D-Latch (DLATCH)

When the DLATCH is selected, the D-input is driven by the even LUT output (LUT(2n)), and the G-input is driven by the odd LUT output (LUT(2n+1)), as shown in Figure 42-14.

When the even LUT is disabled (LUTCTRL(2n).ENABLE=0), the latch output will be cleared. The G-input is forced enabled for one more APB clock cycle, and the D-input to zero. In all other cases, the latch output (OUT) is refreshed as shown in Table 42-5.

RS Latch (RS)

When this configuration is selected, the S-input is driven by the even LUT output (LUT(2n)), and the R-input is driven by the odd LUT output (LUT(2n+1)), as shown in Figure 42-17.

When the even LUT is disabled LUTCTRL(2n).ENABLE=0), the latch output will be cleared. The R-input is forced enabled for one more APB clock cycle and S-input to zero. In all other cases, the latch output (OUT) is refreshed as shown in Table 42-6.