42.6.2.1 Initialization

A generic clock (GCLK_CCL) is optionally required to clock the CCL. This clock must be configured and enabled in the Generic Clock Controller (GCLK) before using input events, filter, edge detection or sequential logic. GCLK_CCL is required when input events, a filter, an edge detector, or a sequential sub-module is enabled. Refer to GCLK - Generic Clock Controller for details.

This generic clock is asynchronous to the user interface clock (CLK_CCL_APB).

The following bits are enable-protected, meaning that they can only be written when the corresponding even LUT is disabled (LUTCTRLn.ENABLE=0):

• Sequential Selection bits in the Sequential Control x (SEQCTRLx.SEQSEL) register

The following registers are enable-protected, meaning that they can only be written when the corresponding LUT is disabled (LUTCTRLn.ENABLE=0):

• LUT Control n (LUTCTRLn) register, except the ENABLE bit

Enable-protected bits in the LUTCTRLn registers can be written at the same time as LUTCTRLn.ENABLE is written to '1', but not at the same time as LUTCTRLn.ENABLE is written to '0'.

Enable-protection is denoted by the Enable-Protected property in the register description.