Command interface for the host
debugger supporting:
Chip erase commands to
provide secure transitions between the different Debug Access Levels
(DAL)
Device integrity check of the
NVM memory regions
Debugger read access of the
NVM Configuration rows
CPU Park mode to get access for a
debugger to the resources of the device depending on Debug Access Level (DAL)
PIC32CM LS00/LS60 Added features:
Device integrity checks
Memory and peripheral
security attributions from user configuration stored in NVM Configuration
rows
SHA- or HMAC-based Secure
Boot on Secure Flash (BOOT region) and Non-Secure Callable Flash (BOOT
region)
Device Identity Composition
Engine (DICE) security standard support with Unique Device Secret (UDS)
PIC32CM
LS60 Added features:
ATECC608B-based Secure Boot on Secure Flash (BOOT region) and
Non-Secure Callable Flash (BOOT region)
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
