17.6.3.1 Enabling a Peripheral Clock

Before a Peripheral Clock is enabled, one of the Generators must be enabled (GENCTRLn.GENEN) and selected as source for the Peripheral Channel by setting the Generator Selection bits in the Peripheral Channel Control register (PCHCTRLm.GEN). Any available Generator can be selected as clock source for each Peripheral Channel.

When a Generator has been selected, the peripheral clock is enabled by setting the Channel Enable bit in the Peripheral Channel Control register, PCHCTRLm.CHEN = 1. The PCHCTRLm.CHEN bit must be synchronized to the generic clock domain. PCHCTRLm.CHEN will continue to read as its previous state until the synchronization is complete.

The following figure illustrates SERCOM0 clock distribution:

  • The FDPLL96M is used as clock source
  • The Generic Clock Generator 1 selects the FDPLL96M as clock source
  • The Peripheral Channel (17 for SERCOM0) selects the Generic Clock Generator 1 to generate the Generic Clock: GCLK_SERCOM0_CORE
  • The SERCOM0 user interface is clocked by CLK_SERCOM0_APB
Figure 17-5. SERCOM0 Clock Distribution
This results in the following register configuration:
  • The source oscillator for a generic clock generator 'n' is selected by writing to the Source bit field in the Generator Control n register (GCLK.GENCTRLn.SRC)
  • A Peripheral Channel m can be configured to use a specific Generic Clock Generator by writing to the Generic Clock Generator bit field in the respective Peripheral Channel m register (GCLK.PCHCTRLm.GEN)
  • The Peripheral Channel number, m, is fixed for a given peripheral. See the Mapping table in the description of GCLK.PCHCTRLm.