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Ultra-Low Power, Secure and Enhanced Touch MCU
Ultra-Low Power, Secure and Enhanced Touch MCU
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PIC32CM2532LE00048 PIC32CM2532LE00064 PIC32CM2532LE00100 PIC32CM2532LS00048 PIC32CM2532LS00064 PIC32CM2532LS00100 PIC32CM2532LS60048 PIC32CM2532LS60064 PIC32CM2532LS60100 PIC32CM5164LE00048 PIC32CM5164LE00064 PIC32CM5164LE00100 PIC32CM5164LS00048 PIC32CM5164LS00064 PIC32CM5164LS00100 PIC32CM5164LS60048 PIC32CM5164LS60064 PIC32CM5164LS60100
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  2. 36 Inter-Integrated Circuit (SERCOM I2C)
  3. 36.6 Functional Description
  4. 36.6.2 Basic Operation
  5. 36.6.2.4 I2C Host Operation
  6. 36.6.2.4.1 Host Clock Generation
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  • 512-KB Flash, 64-KB SRAM with TrustZone, Crypto & Enhanced PTC
  • 1 Configuration Summary
  • 2 Ordering Information
  • 3 Block Diagram
  • 4 Pinout and Packaging
  • 5 Signal Descriptions List
  • 6 Power Supplies
  • 7 Device Start-up
  • 8 Product Mapping
  • 9 Peripherals
  • 10 Memories
  • 11 Processor and Architecture
  • 12 PIC32CM LS00/LS60 Specific Security Features
  • 13 Boot ROM
  • 14 Implementation Defined Attribution Unit (IDAU)
  • 15 Peripheral Access Controller (PAC)
  • 16 Device Service Unit (DSU)
  • 17 Generic Clock Controller (GCLK)

  • 18 Main Clock (MCLK)
  • 19 32.768 kHz Oscillators Controller (OSC32KCTRL)
  • 20 Oscillators Controller (OSCCTRL)
  • 21 Supply Controller (SUPC)
  • 22 Power Manager (PM)
  • 23 Reset Controller (RSTC)
  • 24 Watchdog Timer (WDT)
  • 25 Real-Time Counter (RTC)
  • 26 Frequency Meter (FREQM)
  • 27 Direct Memory Access Controller (DMAC)
  • 28 External Interrupt Controller (EIC)
  • 29 Non-volatile Memory Controller (NVMCTRL)
  • 30 TrustRAM (TRAM)
  • 31 I/O Pin Controller (PORT)
  • 32 Event System (EVSYS)
  • 33 Serial Communication Interface (SERCOM)
  • 34 Universal Synchronous and Asynchronous Receiver-Transmitter (SERCOM USART)
  • 35 Serial Peripheral Interface (SERCOM SPI)
  • 36 Inter-Integrated Circuit (SERCOM I2C)
    • 36.1 Overview
    • 36.2 Features
    • 36.3 Block Diagram
    • 36.4 Signal Description
    • 36.5 Peripheral Dependencies
    • 36.6 Functional Description
      • 36.6.1 Principle of Operation
      • 36.6.2 Basic Operation
        • 36.6.2.1 Initialization
        • 36.6.2.2 Enabling, Disabling, and Resetting
        • 36.6.2.3 I2C Bus State Logic
        • 36.6.2.4 I2C Host Operation
          • 36.6.2.4.1 Host Clock Generation
            • 36.6.2.4.1.1 Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus)
            • 36.6.2.4.1.2 Host Clock Generation (High-Speed Mode)
          • 36.6.2.4.2 Transmitting Address Packets
          • 36.6.2.4.3 Transmitting Data Packets
          • 36.6.2.4.4 Receiving Data Packets (SCLSM=0)
          • 36.6.2.4.5 Receiving Data Packets (SCLSM=1)
          • 36.6.2.4.6 High-Speed Mode
          • 36.6.2.4.7 10-Bit Addressing
        • 36.6.2.5 I2C Client Operation
      • 36.6.3 Additional Features
      • 36.6.4 DMA, Interrupts and Events
      • 36.6.5 Sleep Mode Operation
      • 36.6.6 Debug Operation
      • 36.6.7 Synchronization
    • 36.7 Register Summary - I2C Client
    • 36.8 Register Summary - I2C Host
  • 37 Inter-IC Sound Controller (I2S)
  • 38 Universal Serial Bus (USB)
  • 39 Timer/Counter (TC)
  • 40 Timer/Counter for Control Applications (TCC)
  • 41 True Random Number Generator (TRNG)
  • 42 Configurable Custom Logic (CCL)
  • 43 Analog Peripherals Considerations
  • 44 Analog-to-Digital Converter (ADC)
  • 45 Analog Comparators (AC)
  • 46 Digital-to-Analog Converter (DAC)
  • 47 Operational Amplifier Controller (OPAMP)
  • 48 Peripheral Touch Controller (PTC)
  • 49 Electrical Characteristics
  • 50 Extended Temperature Electrical Characteristics (125°C)
  • 51 Packaging Information
  • 52 Schematic Checklist
  • 53 Appendix
  • 54 Conventions
  • 55 Acronyms and Abbreviations
  • 56 Data Sheet Revision History
  • Microchip Information

36.6.2.4.1 Host Clock Generation

The SERCOM peripheral supports several I2C bidirectional modes:
  • Standard mode (Sm) up to 100 kHz
  • Fast mode (Fm) up to 400 kHz
  • Fast mode Plus (Fm+) up to 1 MHz
  • High-speed mode (Hs) up to 3.4 MHz
The Host clock configuration for Sm, Fm, and Fm+ are described in Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus). For Hs, refer to Host Clock Generation (High-Speed Mode).

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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