18.1 Overview

The Main Clock (MCLK) controls the synchronous clock generation of the device.

Using a clock provided by the Generic Clock Controller (GCLK_MAIN) or the DFLLULP (CLK_DFLLULP), the Main Clock Controller provides synchronous system clocks to the CPU and the modules connected to the AHBx and the APBx bus. The synchronous system clocks are divided into a number of clock domains.