22.5.5 Standby with Static Power Domain Gating in Details
In Standby Sleep mode, the switchable power domain (PDSW) of a peripheral can remain in active state to perform the peripheral's tasks. This Static Power Domain Gating feature is supported by all peripherals. For some peripherals it must be enabled by writing a Run in Standby bit in the respective Control A register (CTRLA.RUNSTDBY) to '1'. Refer to each peripheral chapter for details.
The following examples illustrate Standby with static Power Domain Gating:
TC0 Standby with Static Power Domain Gating
TC0 peripheral is used in counter operation mode. An interrupt is generated to wake-up the device based on the TC0 peripheral configuration. To make the TC0 peripheral continue to run in Standby Sleep mode, the RUNSTDBY bit is written to '1'.
- Entering Standby mode: As shown in Figure 22-6, PDSW remains active. Refer to Power Domain Controller for details.
- Exiting Standby mode: When conditions are met, the TC0 peripheral generates an interrupt to wake-up the device, and the CPU is able to operate normally and execute the TC0 interrupt handler accordingly.
- Wake-up time:
- The required time to set PDSW to active state has to be considered for the global wake-up time, refer to Wake-Up Time for details.
- In this case, the VDDCORE voltage is still supplied by the main voltage regulator, refer to Regulator Automatic Low Power Mode for details. Thus, global wake-up time is not affected by the regulator.
- In case TC0 is running with a clock provided by the FDPLL96M, DFLL48M or DFLLULP, and the SUPC -> VREGPLL.RUNSTDBY = 1, the PDPLL is kept on, and the global wake-up time is not affected by the VREGPLL regulator. If SUPC -> VREGPLL.RUNSTDBY = 0, the time required to set the PDPLL to active state has to be considered for the global wake-up time.
EIC in Standby with Static Power Domain Gating
In this example, EIC peripheral is used to detect an edge condition to generate interrupt to the CPU. An External interrupt pin is filtered by the CLK_ULP32K clock, GCLK peripheral is not used. Refer to Chapter External Interrupt Controller (EIC) for details. The EIC peripheral is located in the power domain PDAO (which is not switchable), and there is no RUNSTDBY bit in the EIC peripheral.
- Entering Standby mode: As shown in Figure 22-7, the switchable power domain is set in retention state by the Power Manager peripheral. The low power regulator supplies the VDDCORE voltage level. The PDPLL is shut-off if no clock requests are present.
- Exiting Standby mode: When conditions are met, the EIC peripheral generates an interrupt to wake the device up. Successively, the PM peripheral sets PDSW to active state, and the main voltage regulator restarts. In the same way, if the CPU is clocked by any clock source from the PDPLL power domain, the VREGPLL regulator restarts. Once PDSW and PDPLL are in active state and both the main voltage and VREGPLL regulators are ready, the CPU is able to operate normally and execute the EIC interrupt handler accordingly.
-
Wake-up time:
- The required time to set the switchable power domains to active state has to be considered for the global wake-up time, refer to Wake-Up Time for details.
- When in standby Sleep mode, the GCLK peripheral is not used, allowing the VDDCORE to be supplied by the low power regulator to reduce consumption, see Regulator Automatic Low Power Mode. In the same way, if no peripheral is requesting one of the FDPLL96M, DFLL48M or DFLLULP clock sources, the VREGPLL regulator is not required, and it will be internally disabled to save power if SUPC -> VREGPLL.RUNSTDBY = 0. Consequently, main voltage regulator wake-up time has to be considered for the global wake-up time as shown in Figure 22-7.
