33.6.1 Principle of Operation

The SERCOM has four internal pads, PAD[3:0], and the signals from I2C, SPI, and USART are routed through these SERCOM pads through a multiplexer. The configuration of the multiplexer is available from the different SERCOM modes. For additional informaton, refer to these chapters:

The SERCOM uses up to two generic clocks: GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW. The core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while working as a Host. The slow clock (GCLK_SERCOMx_SLOW) is only required for certain functions. Refer to the specific mode chapters for additional information.

These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the SERCOM.

The basic structure of the SERCOM serial engine is shown in the following figure. Labels in capital letters are synchronous to the system clock and accessible by the CPU; labels in lowercase letters can be configured to run on the GCLK_SERCOMx_CORE clock or an external clock.

Figure 33-2. SERCOM Serial Engine

The transmitter consists of a minimum of 8-bytes write buffer and a Shift register.

The receiver consists of a minimum of 8-bytes receive buffer and a Shift register.

The Baud Rate Generator (BRG) is capable of running on the GCLK_SERCOMx_CORE clock or an external clock.

Address matching logic is included for SPI and I2C operation.