21.2 Features

  • Voltage Regulators System
    • Main voltage regulator: LDO or Buck Converter in Active mode (MAINVREG)
    • LDO regulator for the FDPLL96M, DFLL48M and DFLLULP clock sources (VREGPLL)
    • Low-Power voltage regulator in Standby mode (LPVREG)
    • Adjustable VDDCORE and VDDPLL to the Sleep mode or the performance level
    • Controlled VDDCORE and VDDPLL voltage slope when changing VDDCORE and VDDPLL respectively
  • Voltage Reference System
    • Reference voltage for ADC and DAC
  • 3.3V Brown-Out Detector (BOD33)
    • Programmable threshold
    • Threshold value loaded from NVM User Row at start-up
    • Triggers resets or interrupts or event. Action loaded from NVM User Row
    • Operating modes:
      • Continuous mode
      • Sampled mode for low power applications with programmable sample frequency
    • Hysteresis value from Flash User Calibration
  • 1.2V Brown-Out Detectors (BOD12 and BOD12PLL)
    • Internal non-configurable Brown-Out Detector for VDDCORE
    • Internal non-configurable Brown-Out Detector for VDDPLL