36.8.1 Control A

Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits

Bit 3130292827262524 
  LOWTOUTENINACTOUT[1:0]SCLSM SPEED[1:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 2322212019181716 
 SEXTTOENMEXTTOENSDAHOLD[1:0]   PINOUT 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 RUNSTDBY  MODE[2:0]ENABLESWRST 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 30 – LOWTOUTEN SCL Low Time-Out Enable

This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the host will release its clock hold, if enabled, and complete the current transaction. A stop condition will automatically be transmitted.

INTFLAG.SB or INTFLAG.MB will be set as normal, but the clock hold will be released. The STATUS.LOWTOUT and STATUS.BUSERR status bits will be set.

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0Time-out disabled.
1Time-out enabled.

Bits 29:28 – INACTOUT[1:0] Inactive Time-Out

If the inactive bus time-out is enabled and the bus is inactive for longer than the time-out setting, the bus state logic will be set to idle. An inactive bus arise when either an I2C host or client is holding the SCL low.

Enabling this option is necessary for SMBus compatibility, but can also be used in a non-SMBus set-up.

Calculated time-out periods are based on a 100kHz baud rate.

Note: This bit field is enable-protected. This bit field is not synchronized.
ValueNameDescription
0x0DISDisabled
0x155US5-6 SCL cycle time-out (50-60µs)
0x2105US10-11 SCL cycle time-out (100-110µs)
0x3205US20-21 SCL cycle time-out (200-210µs)

Bit 27 – SCLSM SCL Clock Stretch Mode

This bit controls when SCL will be stretched for software interaction.

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0SCL stretch according to Figure 36-5.
1SCL stretch only after ACK bit, Figure 36-6.

Bits 25:24 – SPEED[1:0] Transfer Speed

These bits define bus speed.

Note: This bit field is enable-protected. This bit field is not synchronized.
ValueNameDescription
0x0SMStandard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz
0x1FMPFast-mode Plus (Fm+) up to 1 MHz
0x2HSHigh-speed mode (Hs-mode) up to 3.4 MHz
0x3-Reserved

Bit 23 – SEXTTOEN Client SCL Low Extend Time-Out

This bit enables the client SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the host will release its clock hold if enabled, and complete the current transaction. A STOP will automatically be transmitted.

SB or MB will be set as normal, but CLKHOLD will be release. The MEXTTOUT and BUSERR status bits will be set.

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0Time-out disabled
1Time-out enabled

Bit 22 – MEXTTOEN Host SCL Low Extend Time-Out

This bit enables the host SCL low extend time-out. If SCL is cumulatively held low for greater than 10ms from START-to-ACK, ACK-to-ACK, or ACK-to-STOP the host will release its clock hold if enabled, and complete the current transaction. A STOP will automatically be transmitted.

SB or MB will be set as normal, but CLKHOLD will be released. The MEXTTOUT and BUSERR status bits will be set.

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0Time-out disabled
1Time-out enabled

Bits 21:20 – SDAHOLD[1:0] SDA Hold Time

These bits define the SDA hold time with respect to the negative edge of SCL.

Note: This bit field is enable-protected. This bit field is not synchronized.
ValueNameDescription
0x0DISDisabled
0x175NS50-100ns hold time
0x2450NS300-600ns hold time
0x3600NS400-800ns hold time

Bit 16 – PINOUT Pin Usage

This bit set the pin usage to either two- or four-wire operation:

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
04-wire operation disabled.
14-wire operation enabled.

Bit 7 – RUNSTDBY Run in Standby

This bit defines the functionality in standby sleep mode.

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0GCLK_SERCOMx_CORE is disabled and the I2C host will not operate in standby sleep mode.
1GCLK_SERCOMx_CORE is enabled in all sleep modes.

Bits 4:2 – MODE[2:0] Operating Mode

These bits must be written to 0x5 to select the I2C host serial communication interface of the SERCOM.

Note: This bit field is enable-protected. This bit field is not synchronized.

Bit 1 – ENABLE Enable

Note:
  1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE synchronization is complete.
  2. This bit is not enable-protected.
ValueDescription
0The peripheral is disabled or being disabled.
1The peripheral is enabled.

Bit 0 – SWRST Software Reset

Writing '0' to this bit has no effect.

Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled.

Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register.

Note:
  1. When the CTRLA.SWRST is written, the user must poll SYNCBUSY.SWRST bit to know when the reset operation is complete.
  2. During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST is cleared by hardware.
  3. This bit is not enable protected.
ValueDescription
0There is no reset operation ongoing.
1The reset operation is ongoing.