9.5.3.1 Overview
Most of the peripherals are composed of one digital bus interface connected to the APB or AHB bus and running from a corresponding clock in the Main Clock domain, and one peripheral core running from the peripheral Generic Clock (GCLK).
Communication between these clock domains must be synchronized. This mechanism is implemented in hardware, so the synchronization process takes place even if the peripheral generic clock is running from the same clock source and on the same frequency as the bus interface.
As shown in the following figure, each register that requires synchronization has its
individual synchronizer and its individual synchronization status bit in the
Synchronization Busy register (SYNCBUSY).
Note: For registers requiring both read- and
write-synchronization, the corresponding bit in SYNCBUSY is shared.
Synchronization is denoted by the "Read-Synchronized” (bits) and "Write-Synchronized” (bits) property in each individual register description.
