3.6.3 MPDDRC Configuration Register

This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.

Name: MPDDRC_CR
Offset: 0x08
Reset: 0x00207024
Property: Read/Write

Bit 3130292827262524 
    CAS_WR[2:0]   
Access R/WR/WR/W 
Reset 000 
Bit 2322212019181716 
 UNALDECODNDQSNB   DQMS 
Access R/WR/WR/WR/WR/W 
Reset 00100 
Bit 15141312111098 
 SUP_DDR3OCD[2:0]  DIS_DLLDIC_DS 
Access R/WR/WR/WR/WR/WR/W 
Reset 011100 
Bit 76543210 
 DLLCAS[2:0]NR[1:0]NC[1:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00100100 

Bits 28:26 – CAS_WR[2:0] CAS Write Latency

This field is unique to DDR3-SDRAM.
ValueNameDescription
5 DDR3_CAS5 DDR3 CAS write latency 5, DLL must be enabled, DLL On mode
6 DDR3_CAS6 DDR3 CAS write latency 6, DLL enabled or not, DLL On/Off mode

Bit 23 – UNAL This bit must always be written to 1.

Bit 22 – DECOD Type of Decoding

ValueNameDescription
0 SEQUENTIAL Method for address mapping where banks alternate at each last DDR-SDRAM page of the current bank.
1 INTERLEAVED Method for address mapping where banks alternate at each DDR-SDRAM end of page of the current bank.

Bit 21 – NDQS Not DQS.

This bit is found in DDR2-SDRAM devices, in Extended Mode register 1. DQS may be used in Single-ended mode or paired with optional complementary signal NDQS.

ValueNameDescription
0 ENABLED 'Not DQS' is enabled.
1 DISABLED 'Not DQS' is disabled.

Bit 20 – NB Number of Banks

ValueNameDescription
0 4_BANKS 4-bank memory devices
1 8_BANKS 8 banks. Only possible when using DDR2-SDRAM,, DDR3-SDRAM devices.

Bit 16 – DQMS Mask Data is Shared

ValueNameDescription
0 NOT_SHARED DQM is not shared with another controller
1 SHARED DQM is shared with another controller

Bit 15 – SUP_DDR3 Supply DDR3-SDRAM or DDR3L-SDRAM

This value is used during the power-up sequence.

ValueDescription
0 1.35V DDR3L-SDRAM is used.
7 1.5V DDR3-SDRAM is used.

Bits 14:12 – OCD[2:0] Off-chip Driver

SDRAM Controller supports only two values for OCD (default calibration and exit from calibration). These values MUST always be programmed during the initialization sequence. The default calibration must be programmed first, after which the exit calibration and maintain settings must be programmed.

This field is found only in the DDR2-SDRAM devices.

ValueNameDescription
0 DDR2_EXITCALIB Exit from OCD Calibration mode and maintain settings
7 DDR2_DEFAULT_CALIB OCD calibration default

Bit 9 – DIS_DLL Disable DLL

This value is used during the power-up sequence. It is only found in DDR2-SDRAM devices and DDR3-SDRAM devices.

ValueDescription
0 Enable DLL.
1 Disable DLL.

Bit 8 – DIC_DS Output Driver Impedance Control (Drive Strength)

This bit name is described as “DS” in some memory data sheets. It defines the output drive strength. This value is used during the power-up sequence.

For DDR3-SDRAM devices, this field is equivalent to ODS, Output Drive Strength.

This bit is found only in DDR2-SDRAM devices and DDR3-SDRAM devices.

ValueNameDescription
0 DDR2_NORMALSTRENGTH_DDR3_RZQ_6 Normal drive strength (DDR2) - RZQ_6 (40 [NOM], DDR3)
1 DDR2_WEAKSTRENGTH_DDR3_RZQ_7 Weak drive strength (DDR2) - RZQ_7 (34 [NOM], DDR3)

Bit 7 – DLL Reset DLL

This bit defines the value of Reset DLL. It is found only in DDR2-SDRAM and DDR3-SDRAM devices.

This value is used during the power-up sequence.

ValueNameDescription
0 RESET_DISABLED Disable DLL reset
1 RESET_ENABLED Enable DLL reset

Bits 6:4 – CAS[2:0] CAS Latency

ValueNameDescription
3 DDR_CAS3 DDR2 CAS Latency 3
4 DDR_CAS4 DDR2 CAS Latency 4
5 DDR_CAS5 DDR2/DDR3 CAS Latency 5
6 DDR_CAS6 DDR3 CAS Latency 6

Bits 3:2 – NR[1:0] Number of Row Bits

ValueNameDescription
0 11_ROW_BITS 11 bits to define the row number, up to 2048 rows
1 12_ROW_BITS 12 bits to define the row number, up to 4096 rows
2 13_ROW_BITS 13 bits to define the row number, up to 8192 rows
3 14_ROW_BITS 14 bits to define the row number, up to 16384 rows

Bits 1:0 – NC[1:0] Number of Column Bits

ValueNameDescription
0 9_COL_BITS 9 bits to define the column number, up to 512 columns, for DDR2/DDR3-SDRAM

1 10_COL_BITS 10 bits to define the column number, up to 1024 columns, for DDR2/DDR3-SDRAM

2 11_COL_BITS 11 bits to define the column number, up to 2048 columns, for DDR2/DDR3-SDRAM

3 12_COL_BITS 12 bits to define the column number, up to 4096 columns, for DDR2/DDR3-SDRAM