3.6.10 MPDDRC DDR3 Timing Calibration Register
Name: | MPDDRC_DDR3_TIM_CAL |
Offset: | 0x30 |
Reset: | 0x00000006 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ZQCS[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
Bits 7:0 – ZQCS[7:0] ZQ Calibration Short
Defines the delay between the ZQ Calibration command and any valid command in number of DDRCK clock cycles.
The number of cycles is between 0 and 255. This field applies to DDR3 devices.