10.1.6.6.1 FLEXCOM TWI Timings
Symbol | Parameter | Conditions | Min | Max | Unit |
---|---|---|---|---|---|
tLOW_TWCK |
TWCK low time | – | See notes (1, 3, 4) | – | µs |
tHIGH_TWCK | TWCK high time | – | See notes (2, 3, 4) | – | µs |
fTWCK | TWCK frequency(5) |
Standard Fast Fast-Mode Plus High-speed Mode | 0 |
0.1 0.4 1 3.4 | MHz |
tHD(STA) |
Hold time (repeated) START condition |
Standard Fast Fast-Mode Plus | tHIGH_TWCK | – | ns |
High-speed Mode |
FLEX_TWI_CWGR.BRSRCCLK = 1: tLOW_TWCK(6) FLEX_TWI_CWGR.BRSRCCLK = 0: 2 x tHIGH_TWCK | – | ns | ||
tSU(STA) | Setup time for a repeated START condition |
Standard Fast Fast-Mode Plus | tLOW_TWCK | – | ns |
High-speed Mode | FLEX_TWI_CWGR.BRSRCCLK = 1: tLOW_TWCK FLEX_TWI_CWGR.BRSRCCLK = 0: 2 x tLOW_TWCK (6) | – | ns | ||
tHD(DAT) | Data hold time |
Standard Fast Fast-Mode Plus | 2 x tMCKx | (HOLD + 3) × tMCKx | ns |
High-speed Mode | 0 |
150 @ fTWCK max = 1.7 MHz 70 @ fTWCK max = 3.4 MHz | ns | ||
tSU(DAT) | Data setup time |
Standard Fast Fast-Mode Plus |
tLOW – (HOLD + 3) × tMCKx | – | ns |
High-speed Mode | tLOW_TWCK | – | ns | ||
tSU(STO) | Setup time for STOP condition |
Standard Fast Fast-Mode Plus |
FLEX_TWI_CWGR.BRSRCCLK = 1: tLOW_TWCK FLEX_TWI_CWGR.BRSRCCLK = 0: tHIGH_TWCK | – | ns |
High-speed Mode |
FLEX_TWI_CWGR.BRSRCCLK = 1: tHIGH+1 FLEX_TWI_CWGR.BRSRCCLK = 0: tHIGH_TWCK | – | ns | ||
tBUF | Bus free time between a STOP and a START condition |
Standard Fast Fast-Mode Plus | tLOW_TWCK | – | ns |
- TWCK low time (tLOW_TWCK) ≥ tLOWmin - t1*tau → HSCLDIV/CLDIV = ( (tLOW_TWCK / tPERIPH)-3) / 2CKDIV or HSCKDIV )
- TWCK high time (tHIGH_TWCK) ≥ tHIGHmin + (t3-t2)*tau → HSCHDIV/CHDIV = ( (tHIGH_TWCK / tPERIPH)-3) / 2CKDIV or HSCKDIV )
- tTWCK = (tLOW_TWCK + t1*tau) + tr(max + (tHIGH_TWCK + (t3-t2)*tau) + tf(max)
- The TWCK low/high time formulae in notes 1 and 2 are for Bit Rate Source Clock (BRSRCCLK) = 0 for all modes and RX Digital Filter (FILT) = 0 for Standard, Fast and FM+ Modes only. See FLEX_TWI_CWGR, FLEX_TWI_HSCWGR and FLEX_TWI_FILTR registers for more details.
- 1.7 MHz (Cbus 400 pF max), 3.4 MHz (Cbus 100 pF max). Timings in the above table involving tLOW_TWCK and/or tHIGH_TWCK may limit the TWCK maximum frequency when interfacing with an I2C client requiring strict I2C timings.
- If computing HSCLDIV and/or HSCHDIV results in 0, tSU(STA) and/or tHD(STA) is equal to 6x tLOW_TWCK and/or 6x tHIGH_TWCK, respectively.
- MCKx refers to the MCK associated with the FLEXCOM. Refer to column Domain Clock in the table “Peripheral Identifiers”.
Symbol | Parameter | Conditions | Min | Max | Unit |
---|---|---|---|---|---|
fTWCK |
TWCK clock frequency | – | – | 3.4 | MHz |
tHD(DAT) | Data hold time |
fTWCK = 1.7 MHZ | 0 | 70 | ns |
fTWCK = 3.4 MHz | 0 | 150 | |||
tSU(DAT) | Data setup time |
fTWCK = 1.7 MHZ fTWCK = 3.4 MHz | 10 | – | ns |